Lattice Semiconductor

Makers of the ispGAL and ispLSI line.

Product comparison matrix

Application Notes
- AN9009 -- GAL16VP8/20VP8: Bus Arbitration Circuit (July 1997)
- AN8033 -- ispLSI 8840 OE and Internal Tristate Configuration (October 1998)
Data Sheets
- CPLDs
  - MACH 4 Family Data Sheet--Including MACH 4A Family Information, (2.34M) 44, 48 (34io+2i), 84, etc...packaging
  - MACH 5 Family Data Sheet--Including MACH 5A Family Information, (504K) 100 to 208 pin.
  - MACH 1 & 2 Family Data Sheet, (919K ISP 44(32io), 68(48io)($11.15 Marshall min Qty 18, same Avnet, $17.49 Arrow min Qty 1), 84, etc.. pins.
- ispGALs
- ispLSIs
  - ispLSI2032 Data Sheet 44 (32io+2i)
- General Digital CrossPoint and Switch
  - ispGDX and ispGDS Architectural Description (April 1998)
  - ispGDS22/18/14 (June 1997)

available from Jameco, Arrow, Avnet, Marshall

See also:

Circuit Celler Ink #65 December 1995 "In-Circuit-Programmable GALs"
http://www.teleport.com/~thandley/Wilbure.htm
Schematic for the download cable.
SRAM Address Generator and Chip Enable Controller intended for use with PIC16Cxx processors using Port D for a data bus and Port E for control. It supports standard memory devices up to 512K Bytes and provides 4 auxiliary Chip Enables. This version has reduced propagation delays and better documentation.
a 28-Bit Programmable Comparator with Bit-Enable ("Don't Care" Bits). It uses an SPI-style serial interface to load the Bit-Enable qualifiers and the Comparator data. This data is compared with the 28 Inputs to generate an Equality Output. Inputs with their corresponding Bit-Enables cleared are ignored. It also provides a Serial Data Output and an Enable Input to support expansion. One application is a 28-Bit Trigger Comparator in a Logic Analyzer. In this version, I was able to `squeeze' 4 more Bits out of the design and reduce the propagation delays from the Comparator Inputs to the Equality Output by 9ns for the 100MHz device.
This is a 32-Bit Buffered Serial Latch. It uses an SPI-style serial interface to load a 32-Bit Shift Register. The 32-Bit Buffered Latch accepts 32 Bits of data clocked in MSB-first on the SDI (Serial Data In) pin. Data is transferred to the 32-Bit Output Latches on the Rising Edge of the LE (Latch Enable) pin. This is similar to four 74xx595s. An Active-Low Global Reset clears all outputs. All pins have active Pull-ups.
This is a 32-Bit Parallel Input, Serial Output, Shift Register with an SPI-style interface. The 32-Bit Inputs are simultaneously transferred to a 32-Bit Shift Register on the Rising Edge of SCLK when LD1/LD2 (Load Data) are High. Data is then clocked out of the Register MSB-first on the SDO (Serial Data Out) pin. All pins have active Pull-ups.
This is a combination 16-Bit Input, Serial Output, Shift Register and Serial Input, 16-Bit Output, Buffered Latch with an SPI-style interface. An Active-Low Global Reset clears all registers. All pins have active Pull-ups. The 16-Bit Inputs are simultaneously transferred to a 16-Bit Shift Register on the Rising Edge of SCLK when LD (Load Data) is High. Data is then clocked out of the Register MSB-first on the SDO (Serial Data Out) pin. The 16-Bit Buffered Latch accepts 16 Bits of data clocked in MSB-first on the SDI (Serial Data In) pin. Data is transferred to the 16-Bit Output Latches on the Rising Edge of the LE (Latch Enable) pin.