058
-
pblank
.
ACLR
=
reset;
059
-
pblank
.
CLK
=
clock;
060
-
pblank
:=
blank;
061
-
062
-
"video
RAM
control
signals
063
-
csb
=
0;
"enable
the
RAM
064
-
web
=
1;
"disable
writing
to
the
RAM
065
-
oeb
=
blank;
"enable
the
RAM
outputs
when
video
is
not
blanked
066
-
"the
video
RAM
address
is
built
from
the
lower
9
bits
of
the
vertical
067
-
"line
counter
and
bits
7
-
2
of
the
horizontal
column
counter
.
068
-
"Each
byte
of
the
RAM
contains
four
2
-
bit
pixels
.
As
an
example,
069
-
"the
byte
at
address
^h1234=^b0001,0010,0011,0100
contains
the
pixels
070
-
"at
(row,col)
of
(^h048,^hD0),(^h048,^hD1),(^h048,^hD2),(^h048,^hD3)
.
071
-
vram
_
addr
=
[vcnt8
..
vcnt0,hcnt7
..
hcnt2];
072
-
073
-
pixrg
.
ACLR
=
reset;
"clear
pixel
register
on
reset
074
-
pixrg
.
CLK
=
clock;
"pixel
clock
controls
changes
in
pixel
register
075
-
"the
pixel
register
is
loaded
with
the
byte
from
the
video
RAM
location
076
-
"when
the
lower
two
bits
of
the
horizontal
counter
are
both
zero
.
077
-
"The
active
pixel
is
in
the
lower
two
bits
of
the
pixel
register
.
078
-
"For
the
next
3
clocks,
the
pixel
register
is
left
-
shifted
by
two
bits
079
-
"to
bring
the
other
pixels
in
the
register
into
the
active
position
.
080
-
WHEN
([hcnt1
..
hcnt0]==^b00)
081
-
THEN
pixrg
:=
vram
_
data
"load
4
pixels
from
RAM
082
-
ELSE
pixrg
:=
[0,0,pixrg7
..
pixrg2];
"left
-
shift
pixel
register
two
bits
083
-
084
-
"color
mapper
that
translates
each
2
-
bit
pixel
into
a
6
-
bit
RGB
value
.
085
-
"when
the
video
signal
is
blanked,
the
RGB
value
is
forced
to
0
.
086
-
rgb
.
ACLR
=
reset;
087
-
rgb
.
CLK
=
clock;
088
-
TRUTH
_
TABLE
([pblank,
pixel]
:>
rgb)
089
-
[
0
,^b00
]
:>
^b110000;
090
-
[
0
,^b01
]
:>
^b001100;
091
-
[
0
,^b10
]
:>
^b000011;
092
-
[
0
,^b11
]
:>
^b111111;
093
-
[
1
,^b00
]
:>
^b000000;
094
-
[
1
,^b01
]
:>
^b000000;
095
-
[
1
,^b10
]
:>
^b000000;
096
-
[
1
,^b11
]
:>
^b000000;
097
-
098
-
END
VGACORE
Listing
2:
ABEL
code
for
a
VGA
signal
generator
.