needs
at
least
nine
bits
of
resolution
.
Each
frame
is
composed
of
528
video
lines
(only
480
are
visible,
the
other
48
are
blanked),
so
a
ten
bit
counter
is
needed
for
the
line
counter
.
Line
21
:
This
is
the
declaration
for
the
eight
-
bit
register
that
stores
the
four
pixels
received
from
the
RAM
.
Lines
22,23
:
This
line
declares
the
video
blanking
signal
and
its
registered
counterpart
that
is
used
in
the
next
pipeline
stage
.
Lines
25
-
31
:
These
lines
define
aliases
for
the
signals
that
were
declared
earlier
.
Not
that
the
current
active
pixel
is
defined
to
be
in
the
lower
two
bits
of
the
pixel
byte
.
Line
35
:
The
length
of
carry
lookahead
is
set
to
one
position,
so
all
adders
that
follow
will
be
of
the
simple,
space
-
efficient
ripple
-
carry
type
.
This
conserves
logic
gates
at
the
expense
of
speed
.
Lines
37,38
:
The
pixel
and
line
counters
are
set
to
zero
when
the
reset
input
is
high
.
The
reset
is
only
activated
at
the
start
of
the
operation
of
the
VGA
generator
circuitry
and
is
not
used
during
the
normal
operations
.
Lines
39,40
:
The
pixel
counter
is
incremented
on
the
rising
edge
of
the
12
MHz
pixel
clock
.
The
vertical
line
counter
is
clocked
by
the
rising
edge
of
the
horizontal
blanking
pulse,
so
it
increments
only
after
a
line
of
pixels
is
completed
.
Lines
42,43
:
The
active
-
low
horizontal
and
vertical
sync
registers
are
set
to
high
values
when
the
reset
input
is
high
.
Lines
44,45
:
The
registered
horizontal
sync
output
is
updated
on
every
pixel
clock
.
The
registered
vertical
sync
output
is
updated
whenever
a
line
of
video
is
completed
.
The
values
that
are
placed
in
these
registers
at
specific
times
are
determined
in
the
statements
which
follow
.
Line
48:
This
line
sets
the
range
for
the
horizontal
pixel
counter
to
be
[0,380]
.
When
the
counter
reaches
380,
it
rolls
over
to
0
.
Thus,
the
counter
has
a
period
of
381
pixel
clocks
.
With
a
pixel
clock
of
12
MHz,
this
translates
to
a
period
of
31
.
75
m
s
.
Line
50:
This
line
determines
the
active
and
inactive
intervals
of
the
registered
horizontal
sync
output
.
The
sync
signal
goes
low
on
the
cycle
after
the
pixel
counter
reaches
291
and
continues
until
the
cycle
after
the
counter
reaches
337
.
This
gives
a
low
horizontal
sync
pulse
of
(337
-
291)=46
pixel
clocks
.
With
a
pixel
clock
of
12
MHz,
this
translates
to
a
low
-
going
horizontal
sync
pulse
of
3
.
83
m
s
.
The
sync
pulse
starts
292
clocks
after
the
line
of
pixels
begins,
which
translates
to
24
.
33
m
s
.
This
is
less
than
the
26
.
11
m
s
we
stated
before
.
The
difference
of
1
.
78
ms
translates
to
21
pixel
clocks
.
This
time
interval
corresponds
to
the
23
blank
pixels
that
are
placed
prior
to
the
256
viewable
pixels
(minus
two
clock
cycles
for
pipelining
delays)
.
Line
52:
This
line
sets
the
range
for
the
vertical
line
counter
to
be
[0,524]
.
When
the
counter
reaches
527,
it
rolls
over
to
0
.
Thus,
the
counter
has
a
period
of
528
lines
.
Since
the
duration
of
a
line
of
pixels
is
31
.
75
m
s,
this
makes
the
frame
interval
equal
to
16
.
76
ms
.
Line
54:
This
line
determines
the
active
and
inactive
intervals
of
the
registered
vertical
sync
output
.
The
sync
signal
goes
low
on
the
cycle
after
the
line
counter
reaches
493
and
continues
until
the
cycle
after
the
counter
reaches
495
.
This
gives
a
low
vertical
sync
pulse
of
(495
-
493)=
2
lines
.
With
a
line
interval
of
31
.
75
m
s,
this
translates
to
a
low
-
going
vertical
sync
pulse
of
63
.
5
m
s
.
The
vertical
sync
pulse
starts
494
´
31
.
75
m
s
=
15
.
68
ms
after
the
beginning
of
the
first
video
line
.
Line
56:
The
activation
of
the
video
blanking
control
signal
is
set
on
this
line
.
The
video
is
blanked
after
256
pixels
on
a
line
are
displayed,
or
after
480
lines
are
displayed
.
Lines
58
-
60:
The
blanking
signal
is
stored
in
a
register
so
it
can
be
used
during
the
next
stage
of
the
pipeline
when
the
color
is
computed
.