stage
3:
The
binary
color
outputs
are
applied
to
the
DAC
which
sets
the
intensity
levels
for
the
monitor’s
color
guns
.
The
actual
pixel
is
painted
on
the
screen
during
this
stage
.
Figure
3:
Pipelining
of
VGA
signal
generation
tasks
.
The
pseudocode
and
pipeline
timing
will
help
us
understand
the
ABEL
code
in
Listing
2:
Line
6:
This
line
declares
an
input
which
will
reset
all
the
other
circuitry
to
a
known
state
.
Line
7:
The
input
for
the
12
MHz
clock
of
the
XS
Board
is
declared
here
.
This
clock
sets
the
maximum
rate
at
which
pixels
can
be
sent
to
the
monitor
.
The
time
interval
within
each
line
for
transmitting
viewable
pixels
is
25
.
17
m
s,
so
this
VGA
generator
circuit
can
only
put
a
maximum
of
25
.
17
ms
´
12
MHz
=
302
pixels
on
each
line
.
For
purposes
of
storing
images
in
the
RAM,
it
is
convenient
to
reduce
this
to
256
pixels
per
line
and
blank
the
remaining
46
pixels
.
Half
of
these
blank
pixels
are
placed
before
the
256
viewable
pixels
and
half
are
placed
after
them
on
a
line
.
This
centers
the
viewable
pixels
between
the
left
and
right
edges
of
the
monitor
screen
.
Lines
8,9:
The
outputs
for
the
horizontal
and
vertical
sync
pulses
are
declared
.
These
outputs
are
registered
to
make
sure
they
are
not
affected
by
combinational
logic
delays
in
the
VGA
generator
circuitry
.
Lines
10
-
12
:
The
outputs
which
control
the
red,
green,
and
blue
color
guns
of
the
monitor
are
declared
here
.
Each
gun
is
controlled
by
two
bits,
so
there
are
four
possible
intensities
for
each
color
.
Thus,
this
circuit
can
produce
4
´
4
´
4
=
64
different
colors
.
Lines
13,14
:
These
lines
declare
the
outputs
for
driving
the
address
lines
of
the
RAM
and
the
inputs
for
receiving
the
data
from
the
RAM
.
Lines
15
-
17
:
These
are
the
declarations
for
the
outputs
which
drive
the
control
lines
of
the
RAM
.
Lines
19,20
:
The
counters
that
store
the
current
horizontal
position
within
a
line
of
pixels
and
the
vertical
position
of
the
line
on
the
screen
are
declared
on
these
lines
.
We
will
call
these
the
horizontal
or
pixel
counter,
and
the
vertical
or
line
counter,
respectively
.
The
line
period
is
31
.
77
m
s
which
is
381
clock
cycles,
so
the
pixel
counter
