/*
send
L
lines
of
video
to
the
monitor
*/
for
line
_
cnt
=1
to
L
/*
send
P
pixels
for
each
line
*/
for
pixel
_
cnt
=1
to
P
/*
get
pixel
data
from
the
RAM
*/
data
=
RAM(
address
)
address
=
address
+
1
/*
RAM
data
byte
contains
4
pixels
*/
for
d
=1
to
4
/*
mask
off
pixel
in
the
lower
two
bits
*/
pixel
=
data
&
00000011
/*
shift
next
pixel
into
lower
two
bits
*/
data
=
data
>>2
/*
get
the
color
for
the
two
-
bit
pixel
*/
color
=
COLOR
_
MAP(
pixel
)
send
color
to
monitor
d
=
d
+
1
/*
increment
by
four
pixels
*/
pixel
_
cnt
=
pixel
_
cnt
+
4
/*
blank
the
monitor
for
H
pixels
*/
for
horiz
_
blank
_
cnt
=1
to
H
color
=
BLANK
send
color
to
monitor
/*
pulse
the
horizontal
sync
at
the
right
time
*/
if
horiz
_
blank
_
cnt
>
HB0
and
horiz
_
blank
_
cnt
<
HB1
hsync
=
0
else
hsync
=
1
horiz
_
blank
_
cnt
=
horiz
_
blank
_
cnt
+
1
line
_
cnt
=
line
_
cnt
+
1
/*
blank
the
monitor
for
V
lines
and
insert
vertical
sync
*/
for
vert
_
blank
_
cnt
=1
to
V
color
=
BLANK
send
color
to
monitor
/*
pulse
the
vertical
sync
at
the
right
time
*/
if
vert
_
blank
_
cnt
>
VB0
and
vert
_
blank
_
cnt
<
VB1
vsync
=
0
else
vsync
=
1
vert
_
blank
_
cnt
=
vert
_
blank
_
cnt
+
1
/*
go
back
to
start
of
picture
in
RAM
*/
address
=
0
Listing
1:
VGA
signal
generation
pseudocode
.
Figure
3
shows
how
the
circuit
pipelines
certain
operations
to
account
for
delays
in
accessing
data
from
the
RAM
.
The
pipeline
has
three
stages:
stage
1:
The
circuit
uses
the
horizontal
and
vertical
counters
to
compute
the
address
where
the
next
pixel
is
found
in
RAM
.
The
counters
are
also
used
to
determine
the
firing
of
the
sync
pulses
and
whether
the
video
should
be
blanked
.
The
pixel
data
from
the
RAM,
blanking
signal,
and
sync
pulses
are
latched
at
the
end
of
this
stage
so
they
can
be
used
in
the
next
stage
.
stage
2:
The
circuit
uses
the
pixel
data
and
the
blanking
signal
to
determine
the
binary
color
outputs
.
These
outputs
are
latched
at
the
end
of
this
stage
.