Devices that meet the mechanical interface requirements of 8.2, the electrical requirements of 8.3.2, and the protocol compatibility requirements of 7.3, but neither the compliance requirements of that subclause nor the additional protocols of 7.4 et al., are referred to as “IEEE 1284-compatible” devices. IEEE 1284- compatible devices are not 1284 compliant, but they meet the minimum requirements for operation in Compatibility Mode with any 1284-compliant device.
The popular parallel port implementations vary widely in the timing of the nStrobe, nAck, and Busy signals. For instance, many existing hosts ignore the nAck signal entirely, relying on Busy to control the flow of data to the peripheral. The IEEE 1284 protocol compatibility requirements are sufficient to ensure operation of an IEEE 1284-compatible device with an IEEE 1284-compliant device, but not to ensure interoperation of two IEEE 1284-compatible devices. Conversely, the IEEE 1284 protocol compliance requirements ensure operation of IEEE 1284-compliant devices with both IEEE 1284-compliant and IEEE 1284- compatible devices.
Historically, the published specifications of the popular variants of the “Centronics-compatible” interface (see Annex C) specified a single “logic high” and a single “logic low” level for devices on both ends of the interface, leaving no operational margin for noise or losses in the connecting cable. In practical applications, the actual operating characteristics often exceeded these minimum requirements.