Universal IO expander (UNIO)

Two ports, one 6 bit control port and one 8 bit io port. The power up reading of the control port (with weak pull up's) tells the UNIO what mode to operate in. Modes that do not use all 6 control port lines are identified because they have the left over lines pulled (or jumpered) low on the circuit board.

initial
reading		 Signals Mode Notes
111111 En, Addr, Data[4] 4 bit by two addressable latch  
011111 -, Addr, Data[4] 4 bit by two addressable latch Lack of clock is compinsated for by watching all lines for 0.5 clock cycles after any change is detected and updateing output pins only after this "settleing time"
1110 11 En, Data[2], -, Addr[2] 2 bit by four addressable latch  
0110 11 -, Data[2], Addr[2] 2 bit by four addressable latch  
101 111 En, -, Data, Addr[0..3] 1 bit by eight addressable latch  
010 111 -, Data, -, Addr[0..3] 1 bit by eight addressable latch  
1111 10 SCK, SI, SO, *CE, 1, 0 SPI  
1011 10 SCK, -, SI+SO, CE, 1, 0 SPI (3 pin) SO connected to SI thru resistor
1111 00 SCK, SI, SO, CE, 0, 0 SPI <-> Serial RX, TX, *CE, are the first three pins of the 8 bit IO port
1111 01 SCK, SI, SO, CE, 0, 1 SPI <-> I2C SCL, SDA, -, *CE are the first  four pins of the 8 bit IO port.
1100 01 SCL, SDA, -, -, 0, 1 I2C Basically a shift register 
1101 01 SCL, SDA, -, *CE, 0, 1 I2C with *CE Several shift registers connect to the same data and clock lines with seperate chip selects
1111 01 SCL, SDA, CLR, *CE, 0, 1 I2C with *CE and CLR Shift register with enable and clear.
1101 00 SCL, SDA, -,*CE, 0 , 0 I2C <-> Serial Allows us to debug I2C interfaces.
  • When the Serial *CE line is asserted, data is copied from RX to SDA and clocked at the baud rate established by an inital "AT" sent to RX with *CE deasserted. Any I2C signals recieved on SDA while the serial *CE is no asserted will be transmitted to TX at 2400 baud or at a rate indicated by an "AT" sent to RX.
  • RX, TX, *CE, are the first three pins of the 8 bit IO port
  • This mode can also be entered from any of the other I2C modes by dropping the last bit of the control port to 0 from 1. Care should be taken because the Serial TX line will immediatly be driven by the chip and the Serial *CE line could drive SDA and SCL if it is held low.
0100 00 -, TX, -, -, 0, 0 Serial Out  
1000 00 RX, -, -, -, 0, 0 Serial In  
0110 00 -, TX,*CE, -, 0, 0 Serial Out with *CE  
1010 00 RX, -, *CE, -, 0, 0 Serial In with *CE  
1100 00 RX, TX, -, -, 0, 0 Serial IO  
1110 00 RX, TX, *CE, -, 0, 0 Serial IO with *CE  

Notice that the first line of the 6 bit control port is the IRQ line.