From the Embedded Processor and Microcontroller primer and FAQ:
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Von-Neumann Architecture
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Microcontrollers based on the Von-Neuman architecture have a single "data"
bus that is used to fetch both instructions and data. Program instructions
and data are stored in a common main memory. When such a controller addresses
main memory, it first fetches an instruction, and then it fetches the data
to support the instruction. The two separate fetches slows up the controller's
operation.
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Harvard Architecture
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Microcontrollers based on the Harvard Architecture have separate data bus
and an instruction bus. This allows execution to occur in parallel. As an
instruction is being "pre-fetched", the current instruction is executing
on the data bus. Once the current instruction is complete, the next instruction
is ready to go. This pre-fetch theoretically allows for much faster execution
than a Von-Neuman architecture, but there is some added silicon complexity.
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CISC
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Almost all of today's microcontrollers are based on the CISC (Complex Instruction
Set Computer) concept. The typical CISC microcontroller has well over 80
instructions, many of them very powerful and very specialized for specific
control tasks. It is quite common for the instructions to all behave quite
differently. Some might only operate on certain address spaces or registers,
and others might only recognize certain addressing modes. The advantages
of the CISC architecture is that many of the instructions are macro-like,
allowing the programmer to use one instruction in place of many simpler
instructions.
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RISC
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The industry trend for microprocessor design is for Reduced Instruction Set
Computers (RISC) designs. This is beginning to spill over into the microntroller
market. By implementing fewer instructions, the chip designed is able to
dedicate some of the precious silicon real-estate for performance enhancing
features. The benefits of RISC design simplicity are a smaller chip, smaller
pin count, and very low power consumption. Among some of the typical features
of a RISC processor: - Harvard architecture (separate buses for instructions
and data) allows simultaneous access of program and data, and overlapping
of some operations for increased processing performance - Instruction pipelining
increases execution speed - Orthogonal (symmetrical) instruction set for
programming simplicity; allows each instruction to operate on any register
or use any addressing mode; instructions have no special combinations,
exceptions, restrictions, or side effects
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SISC
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Actually, a microcontroller is by definition a Reduced Instruction Set Computer
(at least in my opinion). It could really be called a Specific Instruction
Set Computer (SISC). The [original] idea behind the microcontroller was to
limit the capabilities of the CPU itself, allowing a complete computer (memory,
I/O, interrupts, etc) to fit on the available real estate. At the expense
of the more general purpose instructions that make the standard microprocessors
(8088, 68000, 32032) so easy to use, the instruction set was designed for
the specific purpose of control (powerful bit manipulation, easy and efficient
I/O, and so on). Microcontrollers now come with a mind boggling array of
features that aid the control engineer - watchdog timers, sleep/wakeup modes,
power management, powerful I/O channels, and so on. By keeping the instruction
set specific (and reduced), and thus saving valuable real estate, more and
more of these features can be added, while maintaining the economy of the
microcontroller.
Memory use in Harvard system.
Code & Data seperated.
| Program |
<--CPU--> |
Data |
Memory use in
von-Neumann system.
Code & Data on 1 bus
/->
|
C |
P-|
U |
|
\->
|
Program |
Data
|
Program
|
| Data |
Program
|
John von Neumann