prev: ../pwb_reference_designators.htm --
(This file is just a temporary dumping ground for little factoids. Help me out by pointing where on massmind each factoid should go. )
[What to do with useful stuff not directly Protel related ? Is there a FAQ on PWB design in general ?]
Violation
Violated rule:
Broken-Net Constraint
(On the board)
Violating primitive:
Net GND
Warning - net contains unplated pads.
OK, I see that since those holes are unplated, the pad on top is not directly connected to the internal ground plane. But when I run 2 short traces (one on top, one on bottom) to a via that *is* connected to the internal ground plane, I still get this error. I don't think this should be an error.
Abd ul-Rahman Lomax on 2000-08-21 01:53:22 PM ... 8/21/00 -0700, Brad Velander wrote: ... > Just for your reference we use the following pattern. We have two >triangular drawn pads separated by a diagonal gap of 10 mils. The triangular >pad & diagonal gap makes the visual presentation of the shorting jumper >somewhat unique and less likely to be confused with other pads or features. >There is no soldermask between the two pads. Finally we use a round circular >silkscreen around the pads. The [wave] soldering direction is not important if the break is at a 45 degree angle; results will be the same whichever direction is used. To describe the pad set a little more clearly, imagine a square pad. Draw a line from one corner to the opposite corner. That's the break. So that DRC will be respected, underneath the triangular drawn "pads" will be real pad primitives, being the two pads of the shorting component. I would think a 10 mil break would work, because, as described by others, the surface tension of the solder will militate against an imbalanced triangular blob; instead, the symmetrical square blob will hold together, until and unless sufficient solder is sucked off the pad set. One could also use a round "pad" with a similar diagonal break to maximize the surface tension contribution. Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433
Mel Burk on 2000-08-23 09:10:43 AM Another option is to place one of those hook-type SMT test points and then cut that if necessary.
Abd ul-Rahman Lomax on 2000-08-23 02:57:25 PM ... I'll say this, though. In the original application for this question, it appears that the customization needs to be done in the field. I've been a field technician. I'd much rather drill out a hole than fire up my desoldering equipment. Or cutting a wire would be even easier. The hole method would take minimum board space (since a single jumper occupies the area of a single small hole), the wire jumper -- and I believe I have seen appropriately preformed wires -- would take even less equipment and about the same time, plus the change is easily visible and involves no possible copper shavings, an issue on this high-voltage board. If the solder bridge method ... If a field technician is involved, the cost of that technician's time is the largest cost factor here, and minimizing that time should be the primary object, not fabrication cost. I'd go for wire jumpers unless board space were at a premium, or other factors intervened.
Q: What should I specify for pads that will be used for wire bonding ? Do they need to be gold plated ? -- Evan Scarborough 2000-12-15
A1: "I only specified ' flash-gold' to the board maker. ... this gold is very thin ... it is cheaper, to cover the whole board with the gold instead of selective gold. This is not to compare with the gold plating on edge- board connectors." -- Georg Beckmann 2000-12-16
I have a HP report on the issue where one of their meturallogists conducted experimental measurements of the problem. The conclusion was that >3.0% Au by weight would result in unacceptable embrittlement. You could do your own calculations based upon the volume of solder deposited by your screening process. One other conclusion from the report was that for <50uin of Au using regular solder for even PQFP devices did not significantly increase the incidence of embrittlement. Could you use a little less Au plating for your contacts?
-- Brad Velander on 2000-08-21 03:58:57 PM
According to the findings of this study, if you gold is less then 30 micro inches thick then there should not be any solder joint embrittlement using only regular Lead-Tin solder. This equates to the gold being less then 3% by weight of the solder joint, if this volume is not exceeded then there should be no embrittlement problem.The article was titled "Effect of AU on the Reliability of Fine Pitch Surface Mount Solder Joints" by Judith Glazer, HP, Palo Alto, California. It was published in "Proceedings, Surface Mount International Conference, Aug 25 - 29 (1991), San Jose, CA." It was republished in Circuit World 18, pg 41-46 1992 and Surface Mount Technology 4, pgs 15 - 28 (1992).
-- Brad Velander 2002-04-23
You will find some good information at this website under their Design for Manufacturability information Section D: Plating Options.http://www.merix.com/main_res.html
For the aluminum wire bonding the most common finish is Electroless Nickel/Immersion Gold (99.9% Gold). This finish uses <10uinches immersion gold over 150 - 200 uinches low stress nickel. The most amazing thing about this finish is that if you go to Asia for your boards, they are actually cheaper then HASL or Immersion Tin/Silver. I have previously specified 2 - 4 uinches of immersion gold for aluminum wire bonding with no problem.
Also check out the article in their Resource Center titled "Comparison of Electroless Nickel/ Immersion Gold vs Electrolytic Nickel. How do the two metallizations compare?"
Gold is an excellent solderable finish and the gold under the solder is immediately dissolved into the molten solder mixture. If you are using a gold thickness of less then 50uinches (let's say 30uinches to be safe) then you should have no solderability issues. The only issue with gold is that solder and gold form intermetallics that may result in brittle joints and solder joint failures. This only occurs where the gold would make up better then 4% wt Au (gold). By staying well under the 50 uinches of gold you should have no intermettalic problems. (I have heard 'stories' of people moderately flexing their PCBs and a large number of components pop off into mid-air.)
-- Brad Velander 2000-12-18
To: Multiple recipients of list proteledausers <proteledausers at techservinc.com> Subject: RE: [PROTEL EDA USERS]: advice needed about designing for automa ted assembly.. ... I've found this site quite useful. http://www.aimtronics.com/dfm_foyer.cfm Mel Grewell To: Multiple recipients of list proteledausers <proteledausers at techservinc.com> Subject: RE: [PROTEL EDA USERS]: advice needed about designing for automa ted assembly.. ... The little visual targets you are referring to are called fiducials. Here's an article to give a some details. http://www.ipc.org/html/smema3.1.pdf ... I use global fiducials on all boards, and local fiducials on all footprints with pitches below 20mil (like your 0.5mm QFPs). Mark Geddes
Q: What is a double-sided component in P99SE Print Manager ?
I don't know if it will help any, but if I had this problem the first thing I would try is to turn the hardware acceleration of the video card down a few notches. I'm not sure how this is done in NT (or if there is a related option somewhere in NT...), as I'm running Windows 98SE here.In 98SE however right click on the desktop, select properties, click on the settings tab, click on the advanced pushbutton, click on the performance tab. Each "notch" seems to enable/disable certain acceleration features of the card. Text in this dialog box describes some of the effects going from one notch to the next will have.
...
Worth a shot...
---Phil
"Linden Doyle" on 2000-12-06 11:54:41 PM ...I throttled the Acceleration setting back one notch and the runaway scrolling seems to have disappeared (at least on the PCB I'm working on at the moment.
A1: No. ``In my minimal exposure to mechanical CAD packages (ie Autocad LT and SolidWorks) I've found that SolidWorks is Lego for adults and is quite intuitive to use, and much prefer it.'' http://www.desktop-eda.com.au/products/solid.htm download a demo from http://www.desktop-eda.com.au/download/download.htm -- Brendon Slade 2001-01-03
A2: No. ``Take a look at QualECAD View3D: http://www.qualecad.com/ It is a plug in server for Protel 99se that will do what you need.'' -- John Williams 2001-01-03
A: `` First open a window on whatever server (e.g., PCB Editor) you want to change. Then go to the "arrow" menu (Design explorer), Customize...; on Menus tab, click Menu, Edit..., (here's the tricky part) double-click on the Help entry to expand it and scroll down until you see "Right Mouse Click" ... there they all are. You can use the Menu button drop-down to Add new entries, etc.'' -- "Dwight Harm" on 2001-01-04
Eric Albach on 2001-01-04
Please respond to proteledausers at techservinc.com
Subject: Re: [PROTEL EDA USERS]: Imperial <-> Metric & Wheel Mouse
Update:
I found out that you can change multiple parameters by seperating them
with a pipe " | " (shift backslash).
You can change the Snapgrid, Visiblegrid2 and MeasurementUnit etc. all with a
sigle hotkey.
Parameter Example:
SnapGrid=10mil | MeasurementUnit=Imperial | VisibleGrid2=1000mil
Eric Albach wrote:
> This is not quite the answer you want but here is how to make custom
> Snapgrid hotkeys:
>
> Click on the gray DownArrow button next to the File menu in the PCB editor
>
> Click on Preferences
> Shortcut Keys tab
> Menu Button
> Edit
> Menu Button
> Add
> DoubleClick on new Process called [None]
> Select PCB:DocumentPreferences in Process box
> Type SnapGrid=12.5mil into Parameters box
> (or SnapGrid=.125mm)
> (or VisibleGrid1=1000mil)
> (or VisibleGrid2=20mil)
> etc.
> Select the HotKey that you want to use
>
> The C,I,K,N,Y keys seem to be available.
> You could use the I key for 12.5mil, K for .125mm and toggle measurement
> units with the normal Q hotkey.
> In mm mode there seems to be a small offset error of .00021mm on the
> snapgrid.
>
> A slower alternative that has no offset is the G,O hotkey combination for
> Grid,Option where you can type in the value for the snapgrid.
> This way also toggles the measurement units.
> This is still faster than the Document Options unless you want to change
> the visible grids too.
>
> Eric
>
> Rudolf Schaffer wrote:
>
> > Edi,
> >
> > Thank you for your prompt answer.
> >
> > What i want is to flip between 2 differents "Document Options";
> > one for a metric area of the PCB with 0.5mm pitch component(s)
> > and an other for an area with a 50mil BGA for example.
> >
> > At the moment i use 0.125 mm snap grid and 12.5 mil when i move
> > into the imperial area. (Visible grids are also differents).
> > To move from metric to imperial areas, i am obliged (for the moment..)
> > to edit EACH time the "Document Options" values!
> > With the shortkey "Q" i only go from 50mil to 1.27mm.
> >
> > I read some time ago a solution using a thin grid common to both
> > systems, but i don't like this option.
> >
> > Good afternoon,
> >
> > Rudi
> >
> > Edi Im Hof wrote:
> >
> > >
> > > The Hotkey 'Q' toggles between metric and imperial
> > >
> > > Edi
Information sheet for PCB Design:
Engineer:
mailto:
voice:
PCB Designer:
mailto:
voice:
Product Family:
PCB Part#:
Rev #:
PCB name:
ECR #:
Work Order #:
Date Required:
Schematic Dir:
Schematic Rev:
Board Information
Reflow / Wave Solder:
Number of Layers:
Stackup:
Critical Placement:
Critical Signals:
Power & Ground Issues:
Board length x width:
Mechanical Notes:
Polygon pours:
Design Notes:
(example notes below)
Pcb Notes for 15-03-001 Rev 1.00:
General
1. Polygon pours should be set to 12 mil clearance.
2. Ensure that gnd pour on top layer does not pour between pins of J103, and under tab of U106
and under pins of U129, U128.
3. Directly connect all mounting holes (as well as TP111) to all gnd polygons on each layer.
Aug. 20/2000
1. Problem: Audio signal from U120-7 to U137-10 is too long and may cause cross talk problems
Solution: Move U120 and associated components closer to U137 - Todd B.
Q: OK, what bevel angle should I specify on that card edge ?
A1: For the angle, I used a template PCB generated from the PCB Wizard in
Protel as a guideline. There are dimensions indicated on the Drill Drawing
layer. This seems to work for me. -- Karen Sampson
A2: Some connectors don't require a bevel. Document the chamfer specified
by the manufacturer of the connector. [paraphrased] -- Phan Le
``I ... use the values stamped on components, example capacitors.... 0.001uF, 0.01uF, 0.1uF would be 102 = 1000pF, 103 = 10,000pF and 104 = 100,000pF'' -- Thomas Tannehill
``The system ... of showing capacitor (or resistor etc) values in the format "value value multiplier" is the convention we use since it simplifies the conversion between the part called up and what actually gets ordered from the component manufacturer. Naturally closer tolerance parts just extend the numbers from 3-digits to 4-digits'' -- Jonathan Riley
A1: Just name them both "2" on the footprint. Use the standard 3 pin schematic symbol. [This used to trigger a strange bug in early versions of Protel. Workaround: Whenever you want to "Update PCB" from schematic, first go to the schematic and "clear netlist", then go to the schematic and "Update PCB". Then things work properly. Has anyone seen that bug in Protel99sp6 or later ?]
A2: "Dwight Harm" on 2001-01-30 04:19:02 PM suggests:
I've been happy with a technique recommended some time ago by another list member:1) In the schematic symbol, have a pin for each pad, and assign unique 'numbers' for each pad. For example, I use 1 and 1A for two pins which will coincide.
2) Position the pins on top of each other, so they appear as a single pin, with a single connection point.
3) Each PCB footprint pad has a unique number matching one of the pins.
When you connect a wire to this 'multi-pin', a junction symbol (red dot) will appear due to the multiple pins. All common pins/pads are then part of the same net, and Synchronize works, with no ERC or DRC errors.
I added one twist -- I (mis)use the "circle" style for one pin, and normal for the other(s), so even though the pins coincide, there is a visible line through the circle as a reminder (in case it's needed) that there are multiple pins there.
Dwight.
Q: What to do if a component comes in 2 packages, and I want my board to accept either one ?
A1: ``BTW, sometimes we just pile one chip schematic symbol on top of another when we want both DIP and SMD footprints for the same part schematic stays clean looking and the auto junctions at all the pin ends connect everything up without any fuss.'' -- Dennis Saputelli Dennis Saputelli on 2001-01-30 08:33:27 PM http://www.integratedcontrolsinc.com/
A2:
"Geoff Harland" on 2001-05-29 08:28:32 PM ... Each of two different PCBs that I am currently designing can be fitted with either a through-hole (DPDT) relay or a SM (DPDT) relay, and the footprints for each of these partially overlap. (A SM relay will be fitted by preference, but in the event of supply problems, a through-hole relay can be fitted instead.) I have designated the SM relay as REL1 and the through-hole relay as REL1A; the Designator string for the latter has been concealed. As such, it gives the impression that "REL1" can be either a SM or through-hole relay. I have *also* done a similar thing on each (PCB's corresponding) *schematic* file; the *same* component has been added to each such file *twice*. Again, one of these has a designator of REL1 (and its footprint has been set to the SM footprint), while the other has a (concealed) designator of REL1A (and its footprint has been set to the through-hole footprint). And I have placed *both* of these components in (exactly) the *same* location, so it looks as though (and prints out as) there is only one relay in the schematic file (to wit, "REL1"). (Given that only one relay can be fitted on each actual PCB (due to the overlapping footprints), the above technique is not totally mis-leading, and I have added a note to each schematic file which specifies that either a SM or through-hole relay can be fitted for REL1. And the list of components, and any BOM file produced from each schematic file, lists both REL1 and REL1A, while dots on each pin connected to a wire indicates that it is not a wire connecting to just one pin, but a wire connecting to *more* than one pin.) This technique may not *always* be applicable, but it can be useful in scenarios where multiple footprints are supported (e.g. a through-hole capacitor or SM capacitor, etc). The advantage of this approach is that the netlist file created from each schematic file can be loaded in to the PCB file without any modifications, and no modifications need to be made to the PCB file (netwise) after the netlist file has been loaded into this. (There is a "nuisance factor" in that otherwise unused pins within each device will have a net produced which stipulates that the corresponding pins within each footprint be routed to one another. It probably would be possible to figure out some way to deal with this, but I have not done so to date. I either route the connections concerned, or purge the nets from the PCB file (so the lack of connections between the pads concerned is not reported as a DRC error). But in spite of this consideration, I still think that the above technique has much to be said for it, or at least in many situations (including situations where *all* of the pins are connected to something else, so preventing this "nuisance factor" from being a drawback).) Regards, Geoff Harland. ----------------------------- E-Mail Disclaimer The Information in this e-mail is confidential and may be legally privileged. It is intended solely for the addressee. Access to this e-mail by anyone else is unauthorised. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful. Any opinions or advice contained in this e-mail are confidential and not for public display.
A:
Protel accept that they are unable (yet hopefully) to provide full integrity checking of internal planes.Specifically the Protel software cannot check for: 1) Internal planes with isolated sections caused by free primitives on the plane layer 2) That all plane connections are made by a "sufficiently" large width of copper (no necks that are too narrow) 3) That plane blow-outs around multi-row components have not isolated a connection (or that nearby thermal reliefs are not interfering with each other and other connections). 4) other stuff probably
The warning you got is Protel's quick and dirty check telling you that you should do a careful manual check to ensure that your planes are OK. This warning only occurs when you have some non-automatic (pad blowout/thermal) on an internal plane layer.
Ian Wilson on 2001-01-31 03:53:34 PM
Most people put only 2 things on a plane layer: (1). a no-copper band (``trace'', not ``keep-out'') around the outside of the board to back the copper off from the board edge. Some fabricators will do this for us. (2). Some stack-up text to identify this layer.
A1: ``You edit the menus using the down arrow left of the File menu and select Customize. The right click is part of the current menu tree under Help-Popups-RightMouseClick.'' -- "Darren Moore" on 2001-02-01
A2:
``Or (easier) double click on the menu bar, in an area where there is NO command. Up will come the menu editing utility.In either case, it is critical to note that one must have a design open, or one will get a blank menu structure...
Finally, note that menus go with specific design types. Don't expect a PCB menu mod to transfer to the Schematic editor, or via versa.''
-- Andrew J Jenkins on 2001-02-01 07:02:16 AM
Steve Wiseman (on 2001-02-04 ?) wrote:
``I'm about to stop using the power pintype - it doesn't seem to gain me anything. The plan is to use in & out instead. This will let the netlist checker confirm that there's a driver to each power net, which is something that I don't currently get with the power pintype. (Not that I've just been bitten by power not making it properly into a sheet - oh no...)Can anyone see a down-side to this plan?''
Abd ul-Rahman Lomax (on 2001-02-04) responded:
I'll agree. Multiple power *output* pins is a relatively unusual circumstance and it is easy enough to pop down No-ERCs. The fact that power nets are not checked for a power source is a routine problem. I've seen plenty of schematics without one.
Matt Pobursky on 2001-02-04 also commented:
... I've been defining power output pins as outputs and power input pins as inputs since my Orcad SDT days in the early 80's. I am not a fan of the power pin type, especially hidden pins. I prefer to show all pins of all devices (even NC pins) on all components. It seems to eliminate a lot of questions later in the project from technicians and other engineers who might be reviewing the documentation. Redefining the power pins in this manner has caused me the least amount of grief and still allows me to make sure I have a driving source for all my power inputs on the design. It also allows for "non-power" pins (like the amplifier output you cited) to drive the power input pins of other devices and still generate a clean ERC.Matt Pobursky Maximum Performance Systems
On 12:50 PM 4/02/2001 -0800, Abd ul-Rahman Lomax said:
``...power-input pins are essentially for ERC purposes just like any other input pin. So changing the present power pins to input pins would cause an error message to arise if there were no power source (which would be an output pin or a power pin). This could be done globally for an entire library. I don't see a down side to that.''
Q:
``Talking with different board houses and other PCB designers I get different minimum widths for traces and gaps for high volume production boards. One board house tells me:Copper weight Minimum trace width Minimum gap 1 oz. 5 5 2 oz. 7 7 3 oz. 12 8 4 oz. 12 10I would really be interested in others opinions on this and I'm sure others would be interested also. It might also be interesting to see what others are using for via holes and pad size for the 4 copper weights.''
-- Heart Akerson 2001-03-24 http://www.transverter.net/
A1:
Heavyweight boards!I wouldn't specify anything heavier than 0.5oz copper for fine line work.
The problem stems from the sheer thickness of the copper, and the accompanying side etching that occurs. In order to etch heavy copper thicknesses, the boards must be in the etch tank longer. This means that the exposed sides of the traces are also going to etch away, under the resist. The amount of side etching that occurs is dependent on adjacent copper features. The fabricator won't want fine lines on heavyweight boards 'cause there's a good chance that the trace will totally etch away in the time that it takes other areas of the board to etch.
-- John Haddy on 2001-03-24 05:53:10 PM
A2:
Generally speaking, high weight boards are used for power delivery, and as such have primarily fat traces and a corresponding need for wide gaps (arcing at higher voltages) anyway. The loss of an ability to use narrow traces for support semiconductors is something that IMO one just has to accept, or alternatively compensate for, by use of separate board(s) for ancillary high-density layouts
-- Andrew J Jenkins on 2001-03-23 05:18:29 PM
A1: ``Create a 3 pin part (SCH and PBC) with an A side and a B side.'' -- Bruce Walter on 2001-03-28 06:42:04 PM
A2: ``increased the overlap of the resistors so that the pads separated from each other. True, the body of the resistor in place would be on top of a pad, but this isn't too big of a sin for through hole designs. This method also saved us the confusion on drill files and fabrication drawings with "missing" holes, as well as passing the design rule check. It also had the added advantage of saving me a smidgen of space on a very crowded board.'' -- Martin Spizman on 2001-03-28 07:23:04 PM
Instead of A C B (where C represents a pad shared between two parts) or A A-B B (standard layout; easiest to understand) do this: A B-A B or A B---A B
which takes even less room, so not only is there no space savings, sharing the pad takes up *more* room than not sharing. -- Abd ul-Rahman Lomax on 2001-03-28 09:52:21 PM
Phil Louden on 2001-04-04 10:05:08 AM If you have placed any solder mask layer pads, check that their hole size is 0. I'm not sure if this explains your problem but if they are not 0, they WILL NOT appear in either the generated drill drawing or drill guide (I'm not sure about the hole size editor list). They WILL however, be listed in the drill file and will therefore be drilled in the board. Of greater concern is, that if these pads are placed over areas with inner plane copper and their holes get plated through, you will get shorted planes in your board. The plane clearance rule ignores holes in solder mask layers. (running SP5) Regards Phil Louden
[enhancement: In my opinion, the DRC should flag as an error *every* pad with a nonzero hole size, unless it's on the multilayer. -- David Cary]
Subject: Re: [PEDA] moving a component and tracks at the same time... a primer on selecting objects:
There are many methods of selecting an object.
(1) One may double-click on object to pull of the edit dialog and check the selection box. One also has a choice to do this globally at this point.
(2) One may enclose a set of objects by making a selection box (left-mouse-press & hold on one corner and then move cursor to the other corner and release).
(3) One may shift-left-mouse-click on the object.
(4) One may use one of the Edit/Select commands.
(5) One may use Edit/Query Manager to make complex global selections.
But the most common and usually the fastest and certainly the most flexible are steps (2) and (3).
To select multiple objects by making cumulative selections, make sure that Tools/Preferences/Extend Selections is checked. Otherwise selecting something by some of the methods above will deselect everything else.
Any discussion of selection in Protel is incomplete without this:
When preparing to move a set of selected objects, *always* deselect all (X-A will do it) before making the selections, or use X-O and surround the objects you want to move as in method 2. This will ensure that you have no selected objects outside the ones you want to move. Failing to do this is the major cause of objects being outside the workspace, which can drive you crazy until you realize what is happening. For example, the autorouter may crash or simply refuse to do anything when attempting to route a board with objects outside the workspace.
(A sure sign that there is something outside the workspace is that the box that appears when you are moving complex selections or are moving even small selections quickly enough that screen redraw can't keep up with you will go off-screen.)
To remove such objects, use Edit/Select/Outside to select any objects outside everything you see in the workspace. For some reason, the delete key will not delete these objects until they are inside the workspace. Would that it did, though I prefer to see what I am deleting: it might be some important part of my design, though usually it isn't. Move Selection should do it, or you can place a pad, select it, and move it, which will carry all the outside objects with it so you can move them into the workspace and then delete them.
Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433
[This works consistently in both the schematic editor and the PWB layout editor.] [bug: When a text frame is selected, it looks exactly the same. I wish a yellow outline would appear so I could see whether it is selected or not.]
A:
- 1) If there's only one PCB in the same folder as the current schematic, there's no board prompt at all. (My usual arrangement -- so I was surprised that some indicated they always got the prompt.)
- 2) If there's more than one in the same folder, you get prompted, BUT there's no "create new document" button! (This threw me for a bit, I don't normally see this button & it took me a while to figure out how to get it to appear.)
- 3) If there's [] none in the same folder as the schematic, [but one or more PCBs in a *different* folder] you get the prompt dialog, including the "new document" button.
Frank had case (3), and the new board got created in the same folder, which then put him into case (1), where there's no prompt. Dwight.
-- "Dwight Harm" on 2001-04-06
Q: How come when I shift-clicking a via, nothing happens, even if the via is not locked ? I expected it to yellow-select the (unlocked) via.
A: You have ``multilayer'' turned off. You still see the via on the top, bottom, and inner layers; but you need to turn ``multilayer'' on (with Design | Options) to be able to select vias.
Q: How do I make a paper printout of every footprint in a library ?
A: (see below)
Q: How do I make a list of all the drill sizes used in a library ?
A: (see below)
"Dwight Harm" on 2001-05-29 11:26:40 PM
To: "Protel EDA Forum" Subject: Re: [PEDA] pcb libraries David Cary -- Geoff's description would be a good addition to the FAQ! For step 6, "use one of the commands...", I'd suggest Tools | Interactive Placement | Arrange Within Rectangle, then choose an appropriately-sized area on the PCB. Dwight. -----Original Message----- From: Geoff Harland Sent: Thursday, May 24, 2001 6:39 PM It is possible to copy *all* of the footprints within a Pcb Library file into a Pcb file. I can't remember, offhand, who advised us of how to do this, but start with a blank Pcb file, and follow the following steps: 1. With the Design Manager panel on, select the "Browse PCBLib" Tab while you have the Pcb Library file concerned currently selected. 2. Using the left mouse button, click on the *first* footprint listed in the Design Manager panel. 3. While holding a Shift key down, (left mouse button) click on the *last* footprint listed in the Design Manager panel. *All* of the footprints listed in the Design Manager panel should now be in a highlighted state. 4.While the cusor is located over the area listing these footprints, right-mouse click, then select "Copy" from the resulting popup menu. 5. Switch to the (blank) Pcb file, then invoke the (PCB:)Paste command. One copy of each of the footprints will then be pasted into the Pcb file. 6. Because all of these components are in the same location, space them out. Use the "Select All" command to select everything. (I don't know why, but none of these components are in a selected state when they are *first* pasted into the Pcb file.) Then use one of the commands (I'm not sure which one off-hand, but it is provided) to space out the selected components (which is all of them, because everything on the Pcb was selected previously). You can now generate a report fom the Pcb file and/or produce a printout from the Drill Drawing layer. (Add a string to the Drill Drawing layer, with a caption of .LEGEND (this is a Special String), and preferably place this in the lower left hand corner of the Pcb file. That will then index and count the usage of each hole size used, when the printout from this layer is subsequently produced.) Yet another option is to produce Drill files from the Pcb file; the Drill Report file will list the number of hole sizes used, and the number of times each size is used. Note: After this method of copying all footprints from a Pcb Library file into a Pcb file was first reported (earlier this year?), I updated my PcbAddon Server. It subsequently incorporated a new Process, which sets the Comment field of each component within a Pcb file equal to its Footprint (string). This Process can be useful after creating a Pcb file holding all footprints from a Pcb Library file, as it facilitates identifying each component's footprint. Those wanting to download this Server can do so from the following URL: http://groups.yahoo.com/group/protel-users/files/Addon_Servers_99SE_SP6 /PcbAddon_6_6_1.Zip Note that that Server can only be used if you have SP6 installed. For those who still have SP5 installed instead, a distinct PcbAddon Server has also been released, whose URL is as follows: http://groups.yahoo.com/group/protel-users/files/Addon_Servers_99SE_SP5 /PcbAddon_6_0_1.Zip It is important to install the correct Server, depending upon which SP you currently have installed. (I haven't checked, but you might have to be a member of Yahoo before you can download these files.) Regards, Geoff Harland.
A: Just use C++ Builder. It will compile Delphi code and uses the VCL by default. Best described as a C++ version of Delphi! It will automatically generate C++ headers for VCL based delphi classes/units. -- Scott Ellis on 2001-06-17 09:31:42 PM
"Brad Velander" on 2001-07-24 03:24:05 PM wrote:
... you need to work closely with your customer to meet their expectations for the keypad contacts. The design is typically not difficult or tightly restrained in any fashion except for the expected operation at the user level. There are a lot of issues that relate to the performance which go far beyond the work/no work issues. (i.e., type of device, key response time, is the button well restrained physically or does it roll significantly.) I worked for Advanced Gravis for five years, we did study after study of silicon membrane switches and developed our own requirements but the demands of a PC gamer are significantly different from a photocopier, portable CD player or other devices....
if your boards are manufactured in SE Asia, gold flash over nickel, in SE Asia this is your cheapest finish which will work very well for membrane switches (4 - 8 micro inches gold flash, over 60 - 100 microinches of Nickel, life near infinite, the silicon will deteriorate before the finish is shot).
Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com
I did a screen cap off a power ic data sheet pdf it showed the pinout and a lot of the inner workings, i.e., catch diodes, transistor H bridge it also had all the nice descriptive pin namesI massaged the image and put it into a new sch lib part, stuck some pins on it and voila, it looked great a little big, but greatly explicative of the functionality
now I notice that the image is only a ref to an external file, so it seems that this is not going to be practical, right?
since the image is not in the lib much less in the sch and with a full path name to boot I fear it is not so simple to pass a schematic around ... I can make nice paper ...
i think i have a solution first i moved the .bmp file to the directory holding the lib DDB then i edited the image and stripped the path from the file name
sure enough on the next session start up the image was lost and "error xxx.bmp not found" no path!, good then i imported the bmp into the DDB and now, at least for the moment, it seems to work if this continues to work I think it will be adequate as it can easily travel in the DDB
Dennis Saputelli www.integratedcontrolsinc.com
[FIXME: link to embedding graphics in PWB layout]
A: Yes, It is in the Report menu item. -- Phillip Stevens
A: Library editor Reports | Component gives you a list of pin names/number/type for the current component. -- Terry Harris
A: Another possibility is to double-click on a pin, and set it to a selected state. But *also* invoke the global editing feature so that all pins of the *same type* are *also* selected. So if the pin you are looking at is an input pin, *all* input pins will then be selected. Or if that pin was an output pin instead, then all ouptput pins will then be selected, etc. Doing this will help provide a quick indication of which pins are which. -- Geoff Harland
A: I'd suggest that if you're creating the component, color pins to reflect the pin type. -- Andrew J Jenkins
A. A "Hi-Z" pin is similar to an "Output" pin in that it is *never* an input pin. However, an "Output" pin is always either logic high or logic low. A "Hi-Z" pin differs it that it can be either logic high, logic low, *or* (additionally) in a high impedance state. Various ICs, e.g. 74HC125 (quadruple tri-state buffer) use such pins, and I have personally created a number of components which use such pins. -- Geoff Harland
A. The simplest way is to make it read-only. From the "File Explorer", right-click on the ".ddb" file, select "Properties", and activate "[Y] Read-only | OK". If it's on a Unix-like file server, you might do something like
chmod g-w file.ddb
.
Q: Is it possible to allow several people to view a file as ``guest'' at the same time ? Even while someone is in the middle of editing it ? For example, I might want to open a colleague's DDB to check some dimensions, while he is (or might be) editing it. -- paraphrased from John Haddy 2001-06-07
A. I wish that this common operation ``view, but don't modify'' would be supported by all applications and all modern operating systems. :-(.
One work-around I've recently seen: Some people store each ``.ddb'' file inside individual ``.zip'' archives on the file server. When they view or edit thier PWBs or schematics, they're really working with an uncompressed copy in a temp/ directory on their local hard drive. (With Winzip http://winzip.com/ , opening a ``.ddb'' file inside a ``.zip'' file only takes 1 more double-click than opening a regular ``.ddb'' file). After they exit Protel, Winzip pops up a message something like ``local copy has changed -- want to update the archive ?''. They hit ``No'' if they were just viewing and checking things out, ``Yes'' if they were serious about changing things.
Lots of people can access the same ``.zip'' file at the same time, as long as none of them (or only 1 of them) hit the ``Yes'' button when they exit. -- David Cary
Maybe this could be set up as a design rule, so DRC check would catch dead-end traces and dead-end vias.
On my boards, both ends of every trace segment should connect to *something*, either (a) a pad, (b) a via, (d) another trace segment (not necessarily on the end of that segment).
Also, every via on my boards should connect 2 things together, either (a) a trace on one (signal) layer to a trace on another (signal) layer, or (b) a trace on one (signal) layer to a power plane, or (c) a polygon on one (signal) layer to a power plane.
(Did I miss any useful combinations ?).
Special case: Sometimes I have a long trace segment between 2 components A and B, then I tap off somewhere in the middle of that trace to connect to component C. When I deleted component B, that long trace became a dangling ``dead-end trace''. But I don't want to just delete that long trace segment outright, because I don't want to disconnect A and C. I just want to trim it back to the tap.
This ... server ... Provides a floating resizable window (always on top style) that provides a flipped view of the region around the cursor. The size of the view depends on the size of the floating flip window. Some may find it useful when positioning bottom side designators, for instance. ... If you click on the floating window and hit the 'x' and/or 'y' keys you can toggle the x and y-flips. Hitting <Esc> with the floating flip view window active (clicked) will close it.
-- Ian Wilson on 2001-07-31 08:49:27 AM
Q: How do I install this server ?
A:
Un-zip the files and place the .hlp file into the help subdirectory 'c:\Protel99\Help' on my setup then place the other to files into .ins and .dll into the system subdirectory 'c:\Protel99\System'.Now open Protel click on the server arrow, grey arrow top left next to the file menu. Select servers menu, now right click in the EDA Servers window and choose install select the CSFlipView.ins file that you copied above and then OK.
Now that the server is installed, to run the server [make sure a PCB file is open, then] click on the server arrow, and select run process select 'CSFlipView:ShowFlipWindow' for the Process and 'Show=True|XFlip=True|YFlip=False' for the Parameters click OK and the server should be running.
...
You can change the size of the box by dragging a corner.
-- "Darren Moore" on 2001-07-31 06:25:40 PM
end http://massmind.org/techref/app/protel_unsorted.htm
Questions:
I am using PROTEl99 SE+pack6 on WIN XP+pack2 and I have all "vias" considered zero-size, when I generate Gerber-Drill CAM files? Only the pads w/holes are extracted. Does anyoane know what setting I have wrong?
Thank you, very much, in advance,
Despina
dschlobohm@ems-rfid.com
Code: