Received: from PCH.mit.edu (18.7.21.50) by mail.efplus.com (192.168.0.8) with Microsoft SMTP Server (TLS) id 8.3.485.1; Mon, 15 Mar 2021 01:51:21 -0700 Received: from PCH.MIT.EDU (localhost.localdomain [127.0.0.1]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 12F8fswQ005113; Mon, 15 Mar 2021 04:42:41 -0400 Received: from outgoing-exchange-1.mit.edu (OUTGOING-EXCHANGE-1.MIT.EDU [18.9.28.15]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 12F8fqwF005110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Mon, 15 Mar 2021 04:41:52 -0400 Received: from w92exedge3.exchange.mit.edu (W92EXEDGE3.EXCHANGE.MIT.EDU [18.7.73.15]) by outgoing-exchange-1.mit.edu (8.14.7/8.12.4) with ESMTP id 12F8fmZ9012146 for ; Mon, 15 Mar 2021 04:41:52 -0400 Received: from oc11exhyb3.exchange.mit.edu (18.9.1.99) by w92exedge3.exchange.mit.edu (18.7.73.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 15 Mar 2021 04:41:40 -0400 Received: from oc11exhyb4.exchange.mit.edu (18.9.1.100) by oc11exhyb3.exchange.mit.edu (18.9.1.99) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 15 Mar 2021 04:41:49 -0400 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (104.47.56.40) by oc11exhyb4.exchange.mit.edu (18.9.1.100) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Mon, 15 Mar 2021 04:41:49 -0400 Received: from MW4PR04CA0094.namprd04.prod.outlook.com (2603:10b6:303:83::9) by BN7PR01MB3699.prod.exchangelabs.com (2603:10b6:406:82::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3933.32; Mon, 15 Mar 2021 08:41:48 +0000 Received: from CO1NAM11FT025.eop-nam11.prod.protection.outlook.com (2603:10b6:303:83:cafe::f0) by MW4PR04CA0094.outlook.office365.com (2603:10b6:303:83::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3933.31 via Frontend Transport; Mon, 15 Mar 2021 08:41:48 +0000 Received: from mail-qk1-f169.google.com (209.85.222.169) by CO1NAM11FT025.mail.protection.outlook.com (10.13.175.232) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3933.31 via Frontend Transport; Mon, 15 Mar 2021 08:41:48 +0000 Received: by mail-qk1-f169.google.com with SMTP id d20so30872833qkc.2 for ; Mon, 15 Mar 2021 01:41:48 -0700 (PDT) Received: from [192.168.1.10] ([45.72.217.114]) by smtp.gmail.com with ESMTPSA id o76sm12027380qke.79.2021.03.15.01.41.46 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Mar 2021 01:41:46 -0700 (PDT) From: Jim Ruxton To: "piclist@mit.edu" Sender: "piclist-bounces@mit.edu" Date: Mon, 15 Mar 2021 01:41:44 -0700 Subject: } Re: [PIC] 1 Controller and 18 Peripheral PICs Thread-Topic: } Re: [PIC] 1 Controller and 18 Peripheral PICs Thread-Index: AdcZeF//pMj2X58XTQG0PH20Pg1YOQ== Message-ID: <22fc3363-a6e4-ed6f-6bc7-a9b0bd129ee0@gmail.com> References: <24a1eea7-dbb8-da98-309e-cd4fb87bd4d4@gmail.com> <6d88a2e449f9c633a0ca57efdc178c97.squirrel@mai.hallikainen.org> List-Help: List-Subscribe: , List-Unsubscribe: , In-Reply-To: <6d88a2e449f9c633a0ca57efdc178c97.squirrel@mai.hallikainen.org> Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US Content-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: TempError X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: received-spf: Pass (protection.outlook.com: domain of gmail.com designates 209.85.222.169 as permitted sender) receiver=protection.outlook.com; client-ip=209.85.222.169; helo=mail-qk1-f169.google.com; dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-transfer-encoding:content-language; bh=oOzHp9ZOY5+RaTRffE4EMYt0mxpx3T8JNWss+bLrVHc=; b=LEc32Ql2HQJShr0DFOX0oA6rv8E/7cdM4Vpn2NyiQm6lbnQnA/7f466HiXFTL1bjx+ tEQmcdAlzjFs39MwgK0htCxf6+IPcncTefX62w9giaTPHsDk8oCPa/fQ3UZDYF3254a6 4fKYWp8KRAYbcPrW1cIrXZNPIMPF9aBAYSdRiZHhFEpMtVfTtMr/eOa1w86OATAUfcER 5pApHKeivQCu0dHMEwqzOXaEyAo63TCeS0Q2HgVtGhsBgoHkFGASS4KUI4yKapzII7s/ 6/myFuGfGKkaDJ/OCFmKW4hKg9NAee6vMmkQeimMuPIe7v2a+eXHHl6gqFE/8gGtGXyD vlMA== authentication-results: spf=pass (sender IP is 209.85.222.169) smtp.mailfrom=gmail.com; mit.edu; dkim=pass (signature was verified) header.d=gmail.com; mit.edu; dmarc=pass action=none header.from=gmail.com; user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-received: by 2002:a05:620a:1483:: with SMTP id w3mr23603674qkj.339.1615797707044; Mon, 15 Mar 2021 01:41:47 -0700 (PDT) x-topics: [PIC] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Curious Harold if you typically put a ground plane under you clock lines=20 and size the trace appropriately when using series source termination as=20 described below in order to create a 50 ohm microstrip line or do you=20 just add the series resistor? Would you use something around 33 ohms as=20 the resistor? > One thing to watch out for in any SPI or shift register system is clock > bounce due to transmission line effects. If a single clock line is bused > past several chips, it is really hard to get rid of reflections. My best > solution has been to use a buffer chip (like maybe a 245 or similar with > all inputs tied together at the clock source) and have a separate series > source terminated clock line going out to each device. Series source > termination is really clever. When the clock goes high, it only goes to > 1/2 voltage after the series termination since the transmission line look= s > like infinite length with its characteristic impedance matching the serie= s > termination resistor. This forms a voltage divider dividing the pulse hig= h > voltage by 2. That half voltage step travels down the transmission line > and hits the open end at the chip (chip input is high impedance). The > voltage immediately doubles to the full clock voltage due to the lack of > termination at the destination. The step to full voltage then travels bac= k > towards the source and eventually the voltage at the series termination > resistor jumps up to full voltage. Series source termination with single > destinations has worked well for me. Thanks, Jim --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .