Received: from PCH.mit.edu (18.7.21.50) by mail.efplus.com (192.168.0.8) with Microsoft SMTP Server (TLS) id 8.3.485.1; Sun, 13 Sep 2020 11:05:30 -0700 Received: from PCH.MIT.EDU (localhost.localdomain [127.0.0.1]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 08DHsNtL001448; Sun, 13 Sep 2020 13:54:39 -0400 Received: from outgoing-exchange-3.mit.edu (OUTGOING-EXCHANGE-3.MIT.EDU [18.9.28.13]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 08DHsM9Z001444 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Sun, 13 Sep 2020 13:54:22 -0400 Received: from w92exedge3.exchange.mit.edu (W92EXEDGE3.EXCHANGE.MIT.EDU [18.7.73.15]) by outgoing-exchange-3.mit.edu (8.14.7/8.12.4) with ESMTP id 08DHsJ3b005854 for ; Sun, 13 Sep 2020 13:54:22 -0400 Received: from w92exhyb6.exchange.mit.edu (18.7.71.111) by w92exedge3.exchange.mit.edu (18.7.73.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 13 Sep 2020 13:53:47 -0400 Received: from oc11exhyb4.exchange.mit.edu (18.9.1.100) by w92exhyb6.exchange.mit.edu (18.7.71.111) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 13 Sep 2020 13:53:55 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (104.47.70.107) by oc11exhyb4.exchange.mit.edu (18.9.1.100) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sun, 13 Sep 2020 13:53:55 -0400 Received: from DM5PR13CA0032.namprd13.prod.outlook.com (2603:10b6:3:7b::18) by BYAPR01MB5109.prod.exchangelabs.com (2603:10b6:a03:7d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.17; Sun, 13 Sep 2020 17:53:53 +0000 Received: from DM3NAM03FT009.eop-NAM03.prod.protection.outlook.com (2603:10b6:3:7b:cafe::99) by DM5PR13CA0032.outlook.office365.com (2603:10b6:3:7b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3391.5 via Frontend Transport; Sun, 13 Sep 2020 17:53:53 +0000 Received: from mail-pl1-f171.google.com (209.85.214.171) by DM3NAM03FT009.mail.protection.outlook.com (10.152.82.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Sun, 13 Sep 2020 17:53:53 +0000 Received: by mail-pl1-f171.google.com with SMTP id t6so2099712plz.2 for ; Sun, 13 Sep 2020 10:53:53 -0700 (PDT) From: Luis Moreira To: Microcontroller discussion list - Public. Sender: "piclist-bounces@mit.edu" Date: Sun, 13 Sep 2020 10:57:53 -0700 Subject: Re: [EE] Four Layer Routing Strategy Thread-Topic: [EE] Four Layer Routing Strategy Thread-Index: AdaJ+HgsTmxEv++gTXicL7ztBjMvsQ== Message-ID: References: List-Help: List-Subscribe: , List-Unsubscribe: , In-Reply-To: Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: Pass X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: received-spf: Pass (protection.outlook.com: domain of googlemail.com designates 209.85.214.171 as permitted sender) receiver=protection.outlook.com; client-ip=209.85.214.171; helo=mail-pl1-f171.google.com; dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=PxiH0vuHE14GIy7PCy4ADqcXzowgvC7UBp/mY7ctce0=; b=nzTf8RlX2iuKaG49lm/daqLRNHtmocbQDCPREM8+xay8buHoCyNLIcpZZzbOHeunyE ygQFNg8MA5zcOQtvsFsICNmHDosskwkI/tu3ZIVL7rWolQHcBNE3W7AtuOxks1sMHV2M oKh/mYAR1z/vbKf/xhdrGXV0+AhlhbxXaZxE8E3Mox7w5iMsEdF3BqMH24l2cbbAJEGT ZNDV6v8xuDGoxVoFKHEzlht0KIurN8A6dVgLE2/43EbmmwDuI+5EhoROHqS90afRC76q 3ve5rriCapua6Jdc3UJrE8Sk20yK5JQlvbrzdHhmk+3DGTIdHaLAh94WZqcTD7p8vxoh M16Q== authentication-results: spf=pass (sender IP is 209.85.214.171) smtp.mailfrom=googlemail.com; mit.edu; dkim=pass (signature was verified) header.d=googlemail.com;mit.edu; dmarc=pass action=none header.from=googlemail.com; errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-received: by 2002:a17:90a:4b42:: with SMTP id o2mr5564812pjl.205.1600019632052; Sun, 13 Sep 2020 10:53:52 -0700 (PDT) x-topics: [EE] x-content-filtered-by: Mailman/MimeDel 2.1.6 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Hi Alan, I can see for through-hole components in essence it will be really strait forward. I'm using a traco power DC to DC converter with +15V/ -15V output which is surface mount. It will be on the top layer. After dealing with it's layout requirements, I need then to distribute power as required. so my question was since I'm on the top layer should I try to route power on the top or just use a via to connect into the internal power layer and distribut that way. Also if you have two or 3 voltages on the circuit do you use the power layer to route all three. The 500KHz is the bandwidth of the analogue signal which will be transmitted as a pulse width modulation. This is actually based on an old silabs technical note. Instead of using one of their isolation ICs I'm using fibre optics. I have it working but picked up some noise from the DC to DC converter, do to my not so good layout around it. I need to redesign the board and I'm looking for best options. Thank you. Best Regards Luis On Sun, 13 Sep 2020, 18:28 Alan Pearce, wrote: > > - What do you do with through hole components? > > well, they still have holes through the PCB as done in the past. If > one end is connected to power or ground then the via will connect to > the appropriate plane with thermal reliefs. > > > - how do you deal with a surface mode power supply for the circuit boar= d? > > You will have to place it on the top routing layer but do you > immediately > > get vias to the power layers? > > Are you talking a prebuilt module here or are you looking at regulator > IC? Either way the manufacturer will generally have a recommended PCB > layout. > > > - The vias crossing from the routing layers through the power layers, > will > > this not create other issues? > > Depends on what you regard as issues. Yes on a high speed circuit such > as gigabit video then a via becomes a stub that imparts some extra > inductance that may have to be balanced out in some way, but such > signals are normally run as differential signals as they will be > impedance controlled. You talk of doing 500kHz bandwidth, but what is > your effective carrier frequency, or are you talking in terms of a > 500kbaud signal? In the latter case i wouldn't expect vias to be a > problem, but if you are working with a higher frequency carrier then > you may need to be more careful with routing. > > The thing with vias going through power layers is to make sure you set > up your constraints so that there is sufficient clearance around the > via that production tolerances don't produce a short to the plane due > to drilling tolerances. And ALWAYS use thermal reliefs to any plane or > fill on any layer. > > > On Sun, 13 Sep 2020 at 13:29, Luis Moreira > wrote: > > > > Hi All, > > I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ > > bandwidth analogue optical link at the moment. Obviously noise issues a= re > > very high on my list of issues to avoid. > > The layout strategy you are describing seems very good, but I gave a fe= w > > questions: > > > > - What do you do with through hole components? > > > > - how do you deal with a surface mode power supply for the circuit boar= d? > > You will have to place it on the top routing layer but do you > immediately > > get vias to the power layers? > > > > - The vias crossing from the routing layers through the power layers, > will > > this not create other issues? > > > > On a sightly different subject, on a two layer board I tend to run powe= r > > and routing on the top layer and ground layer mostly as a copper poor o= n > > the bottom layer, is this best practice? > > > > Thank you. > > Best Regards > > Luis > > > > On Sun, 13 Sep 2020, 12:57 Alan Pearce, > > wrote: > > > > > > Ok, sounds like keeping the inner layers as ground and 3.3V > separately > > > > will be the best. No problems there. > > > > > > That is the 'normal' way to do it. And using manhattan routing gives > > > you a good starting point. Once you have the board routed you can loo= k > > > to see where the routing can be tweaked to minimise vias. > > > > > > > One thing about planes though, I once read an article about being > > > > careful using planes, that essentially small ground loops could for= m > > > > in them. > > > > > > Opinion on this has gone back and forth like a leaf in the wind, but > > > one of the most authoritative texts I have seen was an appnote or > > > article from ADI which advocated having one complete ground plane wit= h > > > minimal distinction between digital and analogue ground. It doesn't > > > mean you could mix the digital and analogue parts willy nilly, some > > > care is still needed with relative parts placement. > > > > > > On Sun, 13 Sep 2020 at 02:57, Josh Koffman > wrote: > > > > > > > > Thank you all for the advice! > > > > > > > > Ok, sounds like keeping the inner layers as ground and 3.3V > separately > > > > will be the best. No problems there. > > > > > > > > One thing about planes though, I once read an article about being > > > > careful using planes, that essentially small ground loops could for= m > > > > in them. Since then I've always had my planes as a separate net (ie > > > > not ground), and I connected them to the ground traces strategicall= y. > > > > Each area of pour had only one connection to ground. > > > > > > > > Should I be using the pours a bit more liberally and letting them > join > > > > all the pins on that actual net? That's easily done (actually easie= r > > > > than the way I have been doing it). I'd add thermals in to try to > help > > > > make it easier to solder. > > > > > > > > The board service I've been using lately doesn't allow for > > > > blind/buried vias without a hefty upcharge. I am definitely not at > > > > that level, that's for sure! > > > > > > > > Thank you! > > > > > > > > Josh > > > > -- > > > > A common mistake that people make when trying to design something > > > > completely foolproof is to underestimate the ingenuity of complete > > > > fools. > > > > -Douglas Adams > > > > -- > > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > > > View/change your membership options at > > > > http://mailman.mit.edu/mailman/listinfo/piclist > > > -- > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > > View/change your membership options at > > > http://mailman.mit.edu/mailman/listinfo/piclist > > > > > -- > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > View/change your membership options at > > http://mailman.mit.edu/mailman/listinfo/piclist > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .