Received: from PCH.mit.edu (18.7.21.50) by mail.efplus.com (192.168.0.8) with Microsoft SMTP Server (TLS) id 8.3.485.1; Sun, 13 Sep 2020 05:37:51 -0700 Received: from PCH.MIT.EDU (localhost.localdomain [127.0.0.1]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 08DCRHxU023552; Sun, 13 Sep 2020 08:27:25 -0400 Received: from outgoing-exchange-7.mit.edu (OUTGOING-EXCHANGE-7.MIT.EDU [18.9.28.58]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 08DCRGXD023549 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Sun, 13 Sep 2020 08:27:16 -0400 Received: from w92exedge3.exchange.mit.edu (W92EXEDGE3.EXCHANGE.MIT.EDU [18.7.73.15]) by outgoing-exchange-7.mit.edu (8.14.7/8.12.4) with ESMTP id 08DCR97q017827 for ; Sun, 13 Sep 2020 08:27:16 -0400 Received: from w92expo12.exchange.mit.edu (18.7.74.66) by w92exedge3.exchange.mit.edu (18.7.73.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 13 Sep 2020 08:27:03 -0400 Received: from oc11exhyb3.exchange.mit.edu (18.9.1.99) by w92expo12.exchange.mit.edu (18.7.74.66) with Microsoft SMTP Server (TLS) id 15.0.1365.1; Sun, 13 Sep 2020 08:27:10 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.100) by oc11exhyb3.exchange.mit.edu (18.9.1.99) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Sun, 13 Sep 2020 08:27:10 -0400 Received: from DM5PR15CA0048.namprd15.prod.outlook.com (2603:10b6:4:4b::34) by BN7PR01MB3811.prod.exchangelabs.com (2603:10b6:406:81::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.17; Sun, 13 Sep 2020 12:27:08 +0000 Received: from DM3NAM03FT005.eop-NAM03.prod.protection.outlook.com (2603:10b6:4:4b:cafe::29) by DM5PR15CA0048.outlook.office365.com (2603:10b6:4:4b::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Sun, 13 Sep 2020 12:27:08 +0000 Received: from mail-pl1-f174.google.com (209.85.214.174) by DM3NAM03FT005.mail.protection.outlook.com (10.152.82.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Sun, 13 Sep 2020 12:27:08 +0000 Received: by mail-pl1-f174.google.com with SMTP id j7so3177606plk.11 for ; Sun, 13 Sep 2020 05:27:08 -0700 (PDT) From: Luis Moreira To: Microcontroller discussion list - Public. Sender: "piclist-bounces@mit.edu" Date: Sun, 13 Sep 2020 05:31:08 -0700 Subject: Re: [EE] Four Layer Routing Strategy Thread-Topic: [EE] Four Layer Routing Strategy Thread-Index: AdaJyrJDqTk2yi4KR3iBE3o4Cgtzag== Message-ID: References: List-Help: List-Subscribe: , List-Unsubscribe: , In-Reply-To: Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: Pass X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: received-spf: Pass (protection.outlook.com: domain of googlemail.com designates 209.85.214.174 as permitted sender) receiver=protection.outlook.com; client-ip=209.85.214.174; helo=mail-pl1-f174.google.com; dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=+XrlSmhjJCTTaqPDqU5FZbmumsqBJx8vdqwQN9udnJQ=; b=nk1NhWb6vVfDy/0E02rZ27rvv3sa7RCC+SBHQ6Foqg65iC7Rvyk8OewWjsGAhzrxxC YSNg65C4Ta9k0bHE0k2TArxF0kaDgDuJklHifqi9c5XM/9Krurs9+6NeUEEXFCIZ21cl td1xaBAiu1RbuACWfZEaRObnbFmEetOCdnovvCVGD8kRlMDiKxErBRHL8/9O0QkshksS umw1p8bTgD3AGhHxxrK8d0nYzvsc+dg81LH/UjC7Fy2zmokPUytx0F+PWeuyzWpRskxa z5BL68A/AvQFD/2kuQiXLNfQM2RcLeg/tHnPXGym/M/MdDzbh6NMEheNGlxpWwRsuxTP NUpA== authentication-results: spf=pass (sender IP is 209.85.214.174) smtp.mailfrom=googlemail.com; mit.edu; dkim=pass (signature was verified) header.d=googlemail.com;mit.edu; dmarc=pass action=none header.from=googlemail.com; errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-received: by 2002:a17:90a:2ecb:: with SMTP id h11mr9447544pjs.195.1600000027629; Sun, 13 Sep 2020 05:27:07 -0700 (PDT) x-topics: [EE] x-content-filtered-by: Mailman/MimeDel 2.1.6 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Hi All, I've been doing a bit of PCB layout lately, I'm actually doing a 500KHZ bandwidth analogue optical link at the moment. Obviously noise issues are very high on my list of issues to avoid. The layout strategy you are describing seems very good, but I gave a few questions: - What do you do with through hole components? - how do you deal with a surface mode power supply for the circuit board? You will have to place it on the top routing layer but do you immediately get vias to the power layers? - The vias crossing from the routing layers through the power layers, will this not create other issues? On a sightly different subject, on a two layer board I tend to run power and routing on the top layer and ground layer mostly as a copper poor on the bottom layer, is this best practice? Thank you. Best Regards Luis On Sun, 13 Sep 2020, 12:57 Alan Pearce, wrote: > > Ok, sounds like keeping the inner layers as ground and 3.3V separately > > will be the best. No problems there. > > That is the 'normal' way to do it. And using manhattan routing gives > you a good starting point. Once you have the board routed you can look > to see where the routing can be tweaked to minimise vias. > > > One thing about planes though, I once read an article about being > > careful using planes, that essentially small ground loops could form > > in them. > > Opinion on this has gone back and forth like a leaf in the wind, but > one of the most authoritative texts I have seen was an appnote or > article from ADI which advocated having one complete ground plane with > minimal distinction between digital and analogue ground. It doesn't > mean you could mix the digital and analogue parts willy nilly, some > care is still needed with relative parts placement. > > On Sun, 13 Sep 2020 at 02:57, Josh Koffman wrote: > > > > Thank you all for the advice! > > > > Ok, sounds like keeping the inner layers as ground and 3.3V separately > > will be the best. No problems there. > > > > One thing about planes though, I once read an article about being > > careful using planes, that essentially small ground loops could form > > in them. Since then I've always had my planes as a separate net (ie > > not ground), and I connected them to the ground traces strategically. > > Each area of pour had only one connection to ground. > > > > Should I be using the pours a bit more liberally and letting them join > > all the pins on that actual net? That's easily done (actually easier > > than the way I have been doing it). I'd add thermals in to try to help > > make it easier to solder. > > > > The board service I've been using lately doesn't allow for > > blind/buried vias without a hefty upcharge. I am definitely not at > > that level, that's for sure! > > > > Thank you! > > > > Josh > > -- > > A common mistake that people make when trying to design something > > completely foolproof is to underestimate the ingenuity of complete > > fools. > > -Douglas Adams > > -- > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > View/change your membership options at > > http://mailman.mit.edu/mailman/listinfo/piclist > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .