From: Bob Blick <bobblick@outlook.com>
To: Microcontroller discussion list - Public. <piclist@mit.edu>
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Date: Sat, 12 Sep 2020 10:50:44 -0700
Subject: Re: [EE] Four Layer Routing Strategy
Thread-Topic: [EE] Four Layer Routing Strategy
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Hi Josh,

If you can use layer 2 for ground and layer 3 for +3.3 then you are getting=
 the best possible compromise. I say compromise only because having all you=
r routing on inner layers with buried vias is probably theoretically better=
, but it would be a ridiculously dumb thing in the real world.

Friendly regards, Bob

________________________________________
From: piclist-bounces@mit.edu <piclist-bounces@mit.edu> on behalf of Josh K=
offman
Sent: Saturday, September 12, 2020 10:10 AM
To: Microcontroller discussion list - Public.
Subject: [EE] Four Layer Routing Strategy

Hi all,

I'm working on my first 4 layer board. I feel a bit like I failed
cramming it all into two layers, but I recognize that having so many
vias on every trace would be less than ideal.

I'm using top and bottom for signals, then the inner layers for power.
The board isn't anything crazy RF, just some regular digital signals.
There is some digital audio on the board, so there are a few "medium"
frequency traces.

I plan on using the top inner layer for ground. I'll do it like I
normally do, which is to route the ground traces manually, then do a
pour that connects to the ground trace in one place.

On the bottom inner layer I'm going to route my 3.3V traces. There
will be a lot of free space on that layer.

So the question is, what should I do with the free space on the 3.3V
layer? I could do either a 3.3V pour or another ground pour. I lean
towards another ground pour but I don't want to inadvertently create a
weird capacitor.

Any suggestions? Since this is my first time I'd like to not have to
re-make the board because of this particular error!

Thank you!

Josh


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