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Sender: "piclist-bounces@mit.edu" Date: Sat, 12 Sep 2020 10:10:08 -0700 Subject: [EE] Four Layer Routing Strategy Thread-Topic: [EE] Four Layer Routing Strategy Thread-Index: AdaJKQ7BAZSL087oQkCWPk6NqFNrDw== Message-ID: List-Help: List-Subscribe: , List-Unsubscribe: , Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: Pass X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: received-spf: Pass (protection.outlook.com: domain of gmail.com designates 209.85.166.170 as permitted sender) receiver=protection.outlook.com; client-ip=209.85.166.170; helo=mail-il1-f170.google.com; dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=zDuY24JQ0sAYan/8efjAMmfjPbzlzK02wlY3wyGx1pk=; b=QtQG16HSCvt8BloR0ShTmKHnQOyG6AGiuvjMUSvneaDJzBEptFPRLB1umxXagnbDWY LomElLym/mS0ipzg5jk/6+IjxIsg4kyB6ttT0yiUeHNz03FKMkw01sdwPjHW0ncgL6R5 dwipEwq6Ki1Z/0RYJBHb7rzj6Ebw76gopXDlS/OjlAATKpxCPwZWaY/fpcf3cZPREUCR LZo7SBlzb3bD+PGcEtvlJCGzCLN8ntDoxCDX0FD43fDMaFJCPuic6rvfM0C78+Pqy4xG nyRpxWrHkUdSm9pdvmhn6XeJHU9sfAgeDOr51MZZ/H3/feCd4ahKfaBGlzQ94r/Osf2+ 88vQ== authentication-results: spf=pass (sender IP is 209.85.166.170) smtp.mailfrom=gmail.com; mit.edu; dkim=pass (signature was verified) header.d=gmail.com; mit.edu; dmarc=pass action=none header.from=gmail.com; errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-received: by 2002:a92:d1d0:: with SMTP id u16mr1040224ilg.171.1599930634125; Sat, 12 Sep 2020 10:10:34 -0700 (PDT) x-topics: [EE] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Hi all, I'm working on my first 4 layer board. I feel a bit like I failed cramming it all into two layers, but I recognize that having so many vias on every trace would be less than ideal. I'm using top and bottom for signals, then the inner layers for power. The board isn't anything crazy RF, just some regular digital signals. There is some digital audio on the board, so there are a few "medium" frequency traces. I plan on using the top inner layer for ground. I'll do it like I normally do, which is to route the ground traces manually, then do a pour that connects to the ground trace in one place. On the bottom inner layer I'm going to route my 3.3V traces. There will be a lot of free space on that layer. So the question is, what should I do with the free space on the 3.3V layer? I could do either a 3.3V pour or another ground pour. I lean towards another ground pour but I don't want to inadvertently create a weird capacitor. Any suggestions? Since this is my first time I'd like to not have to re-make the board because of this particular error! Thank you! Josh --=20 A common mistake that people make when trying to design something completely foolproof is to underestimate the ingenuity of complete fools. -Douglas Adams --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .