Received: from PCH.mit.edu (18.7.21.50) by mail.efplus.com (192.168.0.8) with Microsoft SMTP Server (TLS) id 8.3.485.1; Tue, 21 Apr 2020 09:08:58 -0700 Received: from PCH.MIT.EDU (localhost.localdomain [127.0.0.1]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 03LFwYFi032209; Tue, 21 Apr 2020 11:59:08 -0400 Received: from outgoing-exchange-3.mit.edu (OUTGOING-EXCHANGE-3.MIT.EDU [18.9.28.13]) by PCH.mit.edu (8.14.7/8.12.8) with ESMTP id 03LFwWSe032206 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 21 Apr 2020 11:58:32 -0400 Received: from w92exedge3.exchange.mit.edu (W92EXEDGE3.EXCHANGE.MIT.EDU [18.7.73.15]) by outgoing-exchange-3.mit.edu (8.14.7/8.12.4) with ESMTP id 03LFwvGh016455 for ; Tue, 21 Apr 2020 11:59:10 -0400 Received: from oc11exhyb3.exchange.mit.edu (18.9.1.99) by w92exedge3.exchange.mit.edu (18.7.73.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 21 Apr 2020 11:57:37 -0400 Received: from oc11exhyb1.exchange.mit.edu (18.9.1.60) by oc11exhyb3.exchange.mit.edu (18.9.1.99) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 21 Apr 2020 11:57:47 -0400 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.40) by oc11exhyb1.exchange.mit.edu (18.9.1.60) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 21 Apr 2020 11:57:47 -0400 Received: from MWHPR02CA0017.namprd02.prod.outlook.com (2603:10b6:300:4b::27) by MN2PR01MB5390.prod.exchangelabs.com (2603:10b6:208:118::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2921.27; Tue, 21 Apr 2020 15:57:44 +0000 Received: from CO1NAM03FT056.eop-NAM03.prod.protection.outlook.com (2603:10b6:300:4b:cafe::e8) by MWHPR02CA0017.outlook.office365.com (2603:10b6:300:4b::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2937.13 via Frontend Transport; Tue, 21 Apr 2020 15:57:44 +0000 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (40.107.244.116) by CO1NAM03FT056.mail.protection.outlook.com (10.152.81.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2921.25 via Frontend Transport; Tue, 21 Apr 2020 15:57:43 +0000 Received: from BN6PR01MB2403.prod.exchangelabs.com (2603:10b6:404:50::7) by BN6PR01MB2691.prod.exchangelabs.com (2603:10b6:404:cd::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2921.29; Tue, 21 Apr 2020 15:57:40 +0000 Received: from BN6PR01MB2403.prod.exchangelabs.com ([fe80::ac2d:fa96:5f5a:5450]) by BN6PR01MB2403.prod.exchangelabs.com ([fe80::ac2d:fa96:5f5a:5450%3]) with mapi id 15.20.2921.030; Tue, 21 Apr 2020 15:57:40 +0000 From: David Van Horn To: "piclist@mit.edu" Sender: "piclist-bounces@mit.edu" Date: Tue, 21 Apr 2020 08:57:40 -0700 Subject: Re: [EE] LDO reg keeps failing. Looking for suggestions. Thread-Topic: [EE] LDO reg keeps failing. Looking for suggestions. Thread-Index: AQHWF3f7hFkNZ30wykKxlN08AcCYH6iCxMoAgAAFSp6AAOzKAIAABIyI Message-ID: References: <35716fec-1512-6e55-8b3c-d4fe3e9b10aa@gmail.com> , <64c9bf71-2cd6-f378-05e3-8f3375559e50@gmail.com> List-Help: List-Subscribe: , List-Unsubscribe: , In-Reply-To: <64c9bf71-2cd6-f378-05e3-8f3375559e50@gmail.com> Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US Content-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: Pass X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: acceptlanguage: en-US received-spf: None (protection.outlook.com: backcountryaccess.com does not designate permitted sender hosts) dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=k2mdv.onmicrosoft.com; s=selector2-k2mdv-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h4sH12GnTg34vsZgd0c2rWAcJflIkRczE+Ni8nsTABA=; b=cHP+rE8dnzAvWjItamzh26guykpcsbmikOS80s6JOfSrsbQ4QL4dGMrN9Zh71ltP1/7G9bW/QwoO5VRKIPb0NpY3jBe2Cgg7ka7x5+ZHWdgAZu+G+pAhnl1lR1kGChdkvyvUH2XjKutUt4+i6fiAMUS4y2zCG+CW4drScHLAXFo= authentication-results: spf=pass (sender IP is 40.107.244.116) smtp.mailfrom=backcountryaccess.com; mit.edu; dkim=pass (signature was verified) header.d=k2mdv.onmicrosoft.com; mit.edu; dmarc=pass action=none header.from=backcountryaccess.com;compauth=pass reason=100 x-originating-ip: [2601:280:4980:5d60:8434:3802:99af:8bb3] errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-topics: [EE] x-content-filtered-by: Mailman/MimeDel 2.1.6 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 The spinning motor will act as a generator when it's not being driven. and = there are inductive transients to consider. I'd want to see a scope trace= with voltage and current, but the fact that the regulator is dying is stro= ng evidence that this is happening. The reverse polarized diode across the regulator from output to input pins = is easy, cheap, and never a bad idea. ________________________________ From: piclist-bounces@mit.edu on behalf of Isaac = Marino Bavaresco Sent: Tuesday, April 21, 2020 9:38 AM To: piclist@mit.edu Subject: Re: [EE] LDO reg keeps failing. Looking for suggestions. How could Vout raise without the regulator suplying the voltage? Are there any other power sources to the MCU? Em 20/04/2020 22:33, David Van Horn escreveu: > I disagree. > The failure mechanism is well documented, where Vout > Vin. > The point of D8 is to prevent the input pin from being more than a diode = drop below Vout in that situation. > But the problem mechanism here isn't Vin falling, it's Vout rising. > ________________________________ > From: piclist-bounces@mit.edu on behalf of Isaa= c Marino Bavaresco > Sent: Monday, April 20, 2020 7:12 PM > To: piclist@mit.edu > Subject: Re: [EE] LDO reg keeps failing. Looking for suggestions. > > I think D8 is not necessary and may be detrimental in case of reverse > polarity connection. > > If added, D8's cathode should be connected to where D9's cathode is. As > you added D9, D8 is not necessary. > > That configuration used to be suggested in older regulators datasheets > for application where Vin could fall too quickly as result of a sudden > current sink from other circuits, then current would backflow from the > output capacitor to the input pin. With D9 present, that not possible, > the only path to discharge C1 is through the regulator itself. > > Cheers, > > Isaac > > > > > Em 20/04/2020 21:56, James Burkart escreveu: >> Thanks for the info, everyone! >> >> So I added a 4.7uF cap to the output of the reg, added a shunt schottky >> diode across the regulator, and another schottky diode feeding the input >> filter cap. >> >> How does that look? >> >> -- >> Sincerely, >> >> James Burkart >> *925.667.7175* >> >> [image: image.png] >> > > -- > Este email foi escaneado pelo Avast antiv=EDrus. > https://www.avast.com/antivirus > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist -- Este email foi escaneado pelo Avast antiv=EDrus. https://www.avast.com/antivirus -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .