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Sender: "piclist-bounces@mit.edu" Date: Thu, 6 Feb 2020 04:45:19 -0800 Subject: Re: [EE] 78L05 (SO8) overshoot on removal of over-current event? Thread-Topic: [EE] 78L05 (SO8) overshoot on removal of over-current event? Thread-Index: AdXc7QBfZXVHCFtWRgyU2DaP7VShcQ== Message-ID: References: <20200206042012.200670zz9eqi3oss@webmail.ca.inter.net> List-Help: List-Subscribe: , List-Unsubscribe: , In-Reply-To: Reply-To: Microcontroller discussion list - Public. Accept-Language: en-US X-MS-Exchange-Organization-AuthAs: Anonymous X-MS-Exchange-Organization-AuthSource: TS500.efplus4.local X-MS-Has-Attach: X-Auto-Response-Suppress: All X-MS-Exchange-Organization-SenderIdResult: Pass X-MS-Exchange-Organization-PRD: mit.edu X-MS-TNEF-Correlator: received-spf: Pass (protection.outlook.com: domain of gmail.com designates 209.85.167.169 as permitted sender) receiver=protection.outlook.com; client-ip=209.85.167.169; helo=mail-oi1-f169.google.com; dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=T+iLn0Ccw3N/yTw+347iP/mSIM/XAlXRygzRaj8byd4=; b=k/OtlVeIdoPc78o+dzUkizPuVaOY/3GpcwIr91ugupG6GNscMXsNlB0ICnssSm8P+H 4tGc1Y3QBYvRdtVKAh9R4mirtn/HEviCrgCkhlLrf43BWZTvNZ+o86sSkrEpkn3Iia7r ofnOaRmb2jVHx4cxgkmq86sNa7Y4Vnghd1ZpNDBubh1JKRRuKpaBAjGOsqufSGmu64wY j/1q13xJHNRNLRC1I1D84Or+k5T8vT0BC7wfbCJ/f4ECa1UPTV+5hfV3OrRyFQAJEQUY 6ggYCFqw3fQ0TeuVOUdsttcUnk57ooJlkTWnsnDwhlg8JdUL726YA6tVzcCVttIg6Db2 hHJg== authentication-results: spf=pass (sender IP is 209.85.167.169) smtp.mailfrom=gmail.com; mit.edu; dkim=pass (signature was verified) header.d=gmail.com;mit.edu; dmarc=pass action=none header.from=gmail.com;compauth=pass reason=100 errors-to: piclist-bounces@mit.edu list-id: "Microcontroller discussion list - Public." list-post: x-beenthere: piclist@mit.edu x-mailman-version: 2.1.6 x-received: by 2002:a05:6808:b29:: with SMTP id t9mr6729732oij.69.1580993120144; Thu, 06 Feb 2020 04:45:20 -0800 (PST) x-topics: [EE] x-content-filtered-by: Mailman/MimeDel 2.1.6 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Very interesting Russell, I never heard of that before. I see Linear Technology "Application Note 88: Ceramic Input Capacitors Can Cause Overvoltage Transients" talks a little bit about what you mentioned. I suppose a parasitic LC tank circuit could be present on a 2 layer PCB layout if it was arranged the right way. Does the voltage dependant capacitance of certain ceramic dielectrics play a factor in this? -Jason White On Thursday, February 6, 2020, RussellMc wrote: > > > > Another factor of possible relevance - unlikely here but wort noting. > > > Ceramic capacitors subject to a sharp voltage transient may "ring" to > several times their applied voltage and this has been known to cause devi= ce > failures. > Magnitude of ringing depends both on the nature of the transient and the > composition of the capacitor. > Memory says ( and warns me that it may be wrong) that compositions with > poor tempco and voltage coefficient may also be worse in this area. (The > latter makes some sense). > > > Russell > > > > > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 Jason White --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .