What's the status of the following bits:

AD1PCFG bit 14 (PCFG14)
I2C1CON bit 15 (ON)
OSCCON bits 20-19 (PBCLK divisor - there are several notes about a 1:1
ratio requiring additional conditions).   I'm assuming this is still the
divided by 8 from the fuses, but could have been overwritten.

What does the same code do if ran in the simulator?

Have you gotten a meter out and measured the actual voltage on the actual
pin?




On Thu, Nov 7, 2019 at 2:43 PM David Van Horn <
david.vanhorn@backcountryaccess.com> wrote:

>
> Tried this as well in a separate project.
> RA14 always reads high, and I can't even make it toggle!
>
>
> // 8 MHz Xtal, FPLLIDIV =3D DIV_2 sets 4 MHz into PLL
> // FPLLMUL =3D MUL_20 sets 80 MHz output from PLL
> // FPLLODIV =3D DIV_1 sets 80 MHz CPU clock.
>
> // PIC32MX795F512L Configuration Bit Settings
> // 'C' source line config statements
> // DEVCFG3
> #pragma config USERID =3D 0xFFFF          // Enter Hexadecimal value (Ent=
er
> Hexadecimal value)
> #pragma config FSRSSEL =3D PRIORITY_7     // SRS Select (SRS Priority 7)
> #pragma config FMIIEN =3D OFF             // Ethernet RMII/MII Enable (RM=
II
> Enabled)
> #pragma config FETHIO =3D OFF             // Ethernet I/O Pin Select
> (Alternate Ethernet I/O)
> #pragma config FCANIO =3D OFF             // CAN I/O Pin Select (Alternat=
e
> CAN I/O)
> #pragma config FUSBIDIO =3D OFF           // USB USID Selection (Controll=
ed
> by Port Function)
> #pragma config FVBUSONIO =3D OFF           // USB VBUS ON Selection
> (Controlled by USB Module)
>
> // DEVCFG2
> #pragma config FPLLIDIV =3D DIV_2         // PLL Input Divider (2x Divide=
r)
> #pragma config FPLLMUL =3D MUL_20         // PLL Multiplier (20x Multipli=
er)
> #pragma config UPLLIDIV =3D DIV_12        // USB PLL Input Divider (12x
> Divider)
> #pragma config UPLLEN =3D OFF             // USB PLL Enable (Disabled and
> Bypassed)
> #pragma config FPLLODIV =3D DIV_1         // System PLL Output Clock Divi=
der
> (PLL Divide by 1)
>
> // DEVCFG1
> #pragma config FNOSC =3D PRIPLL           // Oscillator Selection Bits
> (Primary Osc w/PLL (XT+,HS+,EC+PLL))
> #pragma config FSOSCEN =3D OFF            // Secondary Oscillator Enable
> (Disabled)
> #pragma config IESO =3D OFF               // Internal/External Switch Ove=
r
> (Disabled)
> #pragma config POSCMOD =3D HS             // Primary Oscillator
> Configuration (HS osc mode)
> #pragma config OSCIOFNC =3D OFF           // CLKO Output Signal Active on
> the OSCO Pin (Disabled)
> #pragma config FPBDIV =3D DIV_8           // Peripheral Clock Divisor
> (Pb_Clk is Sys_Clk/2)
>
> #pragma config FCKSM =3D CSDCMD           // Clock Switching and Monitor
> Selection (Clock Switch Disable, FSCM Disabled)
> #pragma config WDTPS =3D PS1048576        // Watchdog Timer Postscaler
> (1:1048576)
> #pragma config FWDTEN =3D OFF             // Watchdog Timer Enable (WDT
> Disabled (SWDTEN Bit Controls))
>
> // DEVCFG0
> #pragma config DEBUG =3D OFF              // Background Debugger Enable
> (Debugger is disabled)
> #pragma config ICESEL =3D ICS_PGx2        // ICE/ICD Comm Channel Select
> (ICE EMUC2/EMUD2 pins shared with PGC2/PGD2)
> #pragma config PWP =3D OFF                // Program Flash Write Protect
> (Disable)
> #pragma config BWP =3D OFF                // Boot Flash Write Protect bit
> (Protection Disabled)
> #pragma config CP =3D OFF                 // Code Protect (Protection
> Disabled)
>
> // #pragma config statements should precede project file includes.
> // Use project enums instead of #define for ON and OFF.
>
> #include <xc.h>
>
> void main(void) {
>
>     int temp;
>
>     while (1) {
>         //while (1) {
>             TRISACLR =3D (1 << 14); // Output
>             PORTASET =3D (1 << 14); // Toggle
>             PORTACLR =3D (1 << 14); // I/O pin is solidly low when this l=
oop
> runs
>        // }
>         TRISASET =3D (1 << 14); // Input
>         temp =3D PORTA;
>         temp &=3D (1 << 14); //Mask off all but bit 14
>         if (0 =3D=3D temp) {
>             while (1) {
>                 temp++; // hang here if input is low
>             }
>         } else {
>             while (1) {
>                 temp++; // hang here if input is  high
>             }
>         }
>     }
> }
> --
> David VanHorn
> Lead Hardware Engineer
>
> Backcountry Access, Inc.
> 2820 Wilderness Pl, Unit H
> Boulder, CO  80301 USA
> phone: 303-417-1345  x110
> email: david.vanhorn@backcountryaccess.com
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>


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