Tried this as well in a separate project.
RA14 always reads high, and I can't even make it toggle!


// 8 MHz Xtal, FPLLIDIV =3D DIV_2 sets 4 MHz into PLL
// FPLLMUL =3D MUL_20 sets 80 MHz output from PLL
// FPLLODIV =3D DIV_1 sets 80 MHz CPU clock.

// PIC32MX795F512L Configuration Bit Settings
// 'C' source line config statements
// DEVCFG3
#pragma config USERID =3D 0xFFFF          // Enter Hexadecimal value (Enter=
 Hexadecimal value)
#pragma config FSRSSEL =3D PRIORITY_7     // SRS Select (SRS Priority 7)
#pragma config FMIIEN =3D OFF             // Ethernet RMII/MII Enable (RMII=
 Enabled)
#pragma config FETHIO =3D OFF             // Ethernet I/O Pin Select (Alter=
nate Ethernet I/O)
#pragma config FCANIO =3D OFF             // CAN I/O Pin Select (Alternate =
CAN I/O)
#pragma config FUSBIDIO =3D OFF           // USB USID Selection (Controlled=
 by Port Function)
#pragma config FVBUSONIO =3D OFF           // USB VBUS ON Selection (Contro=
lled by USB Module)

// DEVCFG2
#pragma config FPLLIDIV =3D DIV_2         // PLL Input Divider (2x Divider)
#pragma config FPLLMUL =3D MUL_20         // PLL Multiplier (20x Multiplier=
)
#pragma config UPLLIDIV =3D DIV_12        // USB PLL Input Divider (12x Div=
ider)
#pragma config UPLLEN =3D OFF             // USB PLL Enable (Disabled and B=
ypassed)
#pragma config FPLLODIV =3D DIV_1         // System PLL Output Clock Divide=
r (PLL Divide by 1)

// DEVCFG1
#pragma config FNOSC =3D PRIPLL           // Oscillator Selection Bits (Pri=
mary Osc w/PLL (XT+,HS+,EC+PLL))
#pragma config FSOSCEN =3D OFF            // Secondary Oscillator Enable (D=
isabled)
#pragma config IESO =3D OFF               // Internal/External Switch Over =
(Disabled)
#pragma config POSCMOD =3D HS             // Primary Oscillator Configurati=
on (HS osc mode)
#pragma config OSCIOFNC =3D OFF           // CLKO Output Signal Active on t=
he OSCO Pin (Disabled)
#pragma config FPBDIV =3D DIV_8           // Peripheral Clock Divisor (Pb_C=
lk is Sys_Clk/2)

#pragma config FCKSM =3D CSDCMD           // Clock Switching and Monitor Se=
lection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS =3D PS1048576        // Watchdog Timer Postscaler (1:1=
048576)
#pragma config FWDTEN =3D OFF             // Watchdog Timer Enable (WDT Dis=
abled (SWDTEN Bit Controls))

// DEVCFG0
#pragma config DEBUG =3D OFF              // Background Debugger Enable (De=
bugger is disabled)
#pragma config ICESEL =3D ICS_PGx2        // ICE/ICD Comm Channel Select (I=
CE EMUC2/EMUD2 pins shared with PGC2/PGD2)
#pragma config PWP =3D OFF                // Program Flash Write Protect (D=
isable)
#pragma config BWP =3D OFF                // Boot Flash Write Protect bit (=
Protection Disabled)
#pragma config CP =3D OFF                 // Code Protect (Protection Disab=
led)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

void main(void) {

    int temp;

    while (1) {
        //while (1) {
            TRISACLR =3D (1 << 14); // Output
            PORTASET =3D (1 << 14); // Toggle
            PORTACLR =3D (1 << 14); // I/O pin is solidly low when this loo=
p runs
       // }
        TRISASET =3D (1 << 14); // Input
        temp =3D PORTA;
        temp &=3D (1 << 14); //Mask off all but bit 14
        if (0 =3D=3D temp) {
            while (1) {
                temp++; // hang here if input is low
            }
        } else {
            while (1) {
                temp++; // hang here if input is  high
            }
        }
    }
}
--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO =A080301 USA
phone:=A0303-417-1345 =A0x110
email:=A0david.vanhorn@backcountryaccess.com=A0


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