No apparent oscillation on the output. It is byassed with a 100nf cap and on a 4 layer PCB with dedicated power and ground planes. On Thursday, August 29, 2019, Richard Graziano wrote: > If you put a scope on the circuit you may see that this chip is in > oscillation. Did you use bypass capacitors? See if it is oscillating. Th= at > would cause lager current draw. > > > On Thu, Aug 29, 2019 at 9:14 PM Jason White < > whitewaterssoftwareinfo@gmail.com> wrote: > > > Russell that is pretty clever, I am half tempted to give it a try on on= e > of > > my existing prototype boards just to see if it works. The next revision > > will probably get Schmitt trigger ICs since this is (will be) a safety > > sensitive application. > > > > > > On Thursday, August 29, 2019, RussellMc wrote: > > > > > On Fri, 30 Aug 2019 at 09:05, Jason White < > > > whitewaterssoftwareinfo@gmail.com> > > > wrote: > > > > > > > My application is space and power constrained. Is there a logic gat= e > > that > > > > > > does not exhibit this behavior? (100uA in the undefined would be much > > more > > > acceptable than 45mA) Maybe a schmitt trigger would be designed to > > > > > > > > > > > > A Schmitt triggered gate is the obvious solution, as you and others > > have > > > noted. > > > Below I describe an extremely 'naughty' concept which may be able to = be > > > made to work deep-ending on overall situation. > > > This arrangement > > > > > > - may not work at all > > > - may be an utter disaster > > > - may be able to be made to work extremely well > > > > > > Odds are the naughtiness factor exceeds the levels acceptable in a re= al > > > world design :-). > > > > > > "" Solution """: Add a 'suitably sized' resistor in the IC's Vdd line= .. > > > > > > Greatly increased current drain will lower the IC's Vdd thus increasi= ng > > the > > > relative voltage of the inputs relative to the IC. > > > Reduction of current drain will restore the voltages so there is a > > > potential for oscillation depending on time constants. > > > > > > (This "works", if at all, on rising input waveforms. > > > A resistor in the Vss line will achieve a similar result with falling > > > inputs. > > > Both at once (probably) don't work for equal sized resistors. > Assymetric > > > sizing may work in both directions in some cases but, by then magic i= s > > > probably safer). > > > > > > I have never tried this with an IC. > > > But I have successfully added hysteresis in a transistor based circui= t > by > > > adding a small resistor in a current path and using the small pedesta= l > to > > > raise a switching voltage level elsewhere. Not a formal Schmitt per s= e. > > In > > > that case the solution was 'almost elegant' rather than 'naughty' and > > > produced superb results with astonishingly small levels of hysteresis > for > > > the results achieved. (ie calculation suggested that the level that > > worked > > > was far smaller than would be expected to be effective. > > > > > > > > > Russell > > > -- > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > > View/change your membership options at > > > http://mailman.mit.edu/mailman/listinfo/piclist > > > > > > > > > -- > > Jason White > > -- > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > View/change your membership options at > > http://mailman.mit.edu/mailman/listinfo/piclist > > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 Jason White --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .