TI mentions a bus-hold feature, but I'm not sure how available it is.

Implications of Slow or Floating CMOS Inputs, July 1994 to September
2016, SCBA004D

http://www.ti.com/lit/an/scba004d/scba004d.pdf

On Thu, Aug 29, 2019 at 05:01:44PM -0400, Jason White wrote:
> Hello PIC List!
>=20
> I have a design that uses the 74LVC1G332. I found that it draws about 45m=
A
> when 2.2V is applied to all three inputs and does not even get hot. The
> purpose of this gate is to square a very slow moving voltage, the thresho=
ld
> voltage accuracy and stability is unimportant. Hysteresis is not required=
..
>=20
> My application is space and power constrained. Is there a logic gate that
> does not exhibit this behavior? (100uA in the undefined would be much mor=
e
> acceptable than 45mA) Maybe a schmitt trigger would be designed to
> accommodate this?
>=20
> Otherwise I think I will be forced to use a comparator which would add tw=
o
> (or three) resistors to the design for a reference voltage. A single
> transistor solution would probably not be optimal due to the limited gain=
..
>=20
>=20
> Thanks!
> Jason White
> --=20
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--=20
James Cameron
http://quozl.netrek.org/
--=20
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