I saw that in the data sheet, but it also talks about the open drain
outputs allowing to switch voltages higher than VDD, specifically in the
CPP module 21.1.2

*Open-Drain Output Option*
When operating in Output mode (the Compare or PWM modes), the drivers for
the CCPx pins can be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the output to communicate
with external circuits without the need for additional level shifters.

--
Sincerely,

James Burkart
*925.667.7175*


On Mon, Aug 26, 2019 at 2:03 PM Forrest Christian (List Account) <
lists@packetflux.com> wrote:

> Nope:
>
> Section 26.0:
> Voltage on any pin with respect to VSS (except VDD and MCLR)
> ................................................... -0.3V to (VDD + 0.3V)
>
> The NPN you're using is probably the best option.
>
>
>
> On Mon, Aug 26, 2019 at 12:19 PM James Burkart <james@burkartstudios.com>
> wrote:
>
> > I can't find in the datasheet what the maximum voltage allowed on a pin
> > configured as output with open drain. I'd like to switch a P-FET
> configured
> > as a high-side using an OD output on the PIC, where the gate is pulled =
up
> > to 12.6V. Is this OK to do? Currently I'm using a 2n2222 to pull the ga=
te
> > low, but if I could nix it and control the gate directly that would be
> > great!
> >
> > --
> > Sincerely,
> >
> > James Burkart
> > *925.667.7175*
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> >
>
>
> --
> - Forrest
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
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