Nope:

Section 26.0:
Voltage on any pin with respect to VSS (except VDD and MCLR)
.................................................... -0.3V to (VDD + 0.3V)

The NPN you're using is probably the best option.



On Mon, Aug 26, 2019 at 12:19 PM James Burkart <james@burkartstudios.com>
wrote:

> I can't find in the datasheet what the maximum voltage allowed on a pin
> configured as output with open drain. I'd like to switch a P-FET configur=
ed
> as a high-side using an OD output on the PIC, where the gate is pulled up
> to 12.6V. Is this OK to do? Currently I'm using a 2n2222 to pull the gate
> low, but if I could nix it and control the gate directly that would be
> great!
>
> --
> Sincerely,
>
> James Burkart
> *925.667.7175*
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>


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