On Sun, Jun 30, 2019 at 9:01 PM doug metzler wrote= : > > Thank you Manu and Russell for taking the time to go through the schemati= c > and datasheets. > > In answer to your questions > > 1. The part number that you have used in the schematic does not match > the device that you provided in the URL. Assuming that is an error in > the schematic; > > Correct, fat finger. The actual part number is IRLR3636PbF. I used this > part because it is in use in other circuits in our system so is already i= n > the BOM. > > 2. Why in your schematic, you say that the FET needs a saturaton > voltage of 10V ? The MOSFET that's described in the URL is a Logic > Level Drive MOSFET. It needs a max Vgs of 4.5V but you mention a Gate > drive of 10V in your schematic. The datasheet albeit says Vgs max can > go up to 16V. The Vgs curve also shows a Vgs max of about 6V. > > Because of my "it's been my understanding" statement - I've tried to swit= ch > 24V with logic level fets in the past and it hasn't worked as I expected. > My solution was to use a transistor to raise the gate voltage. I'm sur= e > Russell is correct that I'm not reading the datasheet carefully enough. Indeed, what he wrote is right. It does not matter what driver you use .. You need to provide the FET with the proper voltage, All you need to do is identify the total charge required (Qg) and how much current is required for acceptable turn on delays. Iav =3D Qg * freq To provide you the required information, have a look in here. http://www.ti.com/lit/ml/slua618a/slua618a.pdf http://www.efo-power.ru/BROSHURES_CATALOGS/AN-1001_IGBT_and_MOSFET_Drivers_= Correctly_Calculated.pdf Regarding the UCC going up in smoke, something additionally wrong in your implementation probably. Cheers, Manu --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .