Thank you Manu and Russell for taking the time to go through the schematic
and datasheets.

In answer to your questions

1. The part number that you have used in the schematic does not match
the device that you provided in the URL. Assuming that is an error in
the schematic;

Correct, fat finger.  The actual part number is IRLR3636PbF.  I used this
part because it is in use in other circuits in our system so is already in
the BOM.

2. Why in your schematic, you say that the FET needs a saturaton
voltage of 10V ? The MOSFET that's described in the URL is a Logic
Level Drive MOSFET. It needs a max Vgs of 4.5V but you mention a Gate
drive of 10V in your schematic. The datasheet albeit says Vgs max can
go up to 16V. The Vgs curve also shows a Vgs max of about 6V.

Because of my "it's been my understanding" statement - I've tried to switch
24V with logic level fets in the past and it hasn't worked as I expected.
My solution was to use a transistor to raise the gate voltage.    I'm sure
Russell is correct that I'm not reading the datasheet carefully enough.

3. I think a simple totem pole driver would be sufficient to drive the
MOSFET, considering that the datasheet states only a low gate charge
required. Reducing the schematic down, I guess even a simple
transistor could've replaced the entire driver design, for the reason
mentioned at #6 probably.

I was trying to use the UCC chip in leiu of a totem pole driver.  It had 2
inputs and would have resulted in lower parts count and space savings.

4. Why are there no decoupling capacitors on the power rails ?

There are decoupling caps on the target device, but I can put them on this
board if that is your recommendation.

5. Why do you have D2 ?

so that P3 & 4 of U$9 don't push 24V to the output of the UCC.

6. Why do you have C1 ? Vin will rise slowly defined by the RC
constant. Isn't it too large, that it slows down the gate drive and
negates why you have used a gate driver for a logic level FET ?

In an earlier revision I had problems with the way the circuit powered up
(it powered up in the on state rather than the off state) and I solved it
by adding a cap to the gate of one of the FETS,   You are correct that that
cap should have been DNP and only populated if needed.

But I would still like to explore why the UCC exploded.

Thanks,

DougM




On Sat, Jun 29, 2019 at 6:19 AM RussellMc <apptechnz@gmail.com> wrote:

> > It has been my understanding that FETs at high voltages (like 24) don't
> fully open with 3v3 at the gate,
>
> Do not use the "been understanding" technique if you have a datasheet.
>
>
> On datasheet
>
> https://www.infineon.com/dgdl/irlr3636pbf.pdf?fileId=3D5546d462533600a401=
53566d1e122698
> figs 1 2 3 page 3 tell you all you (probably) want to know about gate
> drive.
> 5 VDC should be "very adequate"
>
>
>                 Russell
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