Note that this app note makes a distinction between Cadc (section 4.4) and Cin (section 4.5). It suggests reducing Fsample to help with Cadc and Rin (internal plus external R) in section 4.4 It suggests reducing Fain (the SOURCE frequency) to deal with large Cin (section 4.5). These are completely different effects. The first one (4.4) is the non-obvious one which is related to the sample and hold cap having to charge. The second one (section 4.5) is simply saying that external R and C will form a low-pass filter (duh!) which will filter your signal. On Wed, Aug 22, 2018 at 8:15 AM, Richard wrote: > Okay, I had to refresh my memory. I couldn't (quickly) find the > Microchip document I thought I had read, but I did find an > STMicroelectronics application note, AN1636, Understanding and > Minimising ADC Conversion Errors. Section 4.5 of that AN talks about the > effect of source capacitance. > The charge time of any input capacitance (including parasitic) needs to > be taken into account. If the input C is not fully charged, the voltage > at the analog input will not be the same as the analog source voltage, > skewing the results. Thus, the sample time may have to be adjusted to > compensate for the time needed to charge the input C - plus - the time > need to charge the ADC C. Much ore info in the AN. > > I don't recall if the list will take a link, but here is the url of the A= N: > https://www.st.com/content/ccc/resource/technical/ > document/application_note/9d/56/66/74/4e/97/48/93/CD00004444.pdf/files/ > CD00004444.pdf/jcr:content/translations/en.CD00004444.pdf > > Richard > > > On 8/22/2018 2:47 AM, Sean Breheny wrote: > > But that explanation only makes sense if the parasitic cap were on the > ADC > > side of the sample-and-hold switch. Once you place it externally, it > should > > only help, and the sampling frequency or sample-and-hold aperture are > > pretty immaterial to it. > > > > On Tue, Aug 21, 2018 at 8:08 PM, Richard wrote: > > > >> > >> On 8/21/2018 4:06 PM, Jason White wrote: > >>> A footnote (note 2 in attached image) in the STM32F207 datasheet (pag= e > >> 127) > >>> states that a high capacitance at the ADC input pin can reduce > conversion > >>> accuracy. How exactly should this be interpreted? > >>> > >>> Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth= .. > >> But > >>> will the capacitance affect the internal operation of the ADC? > >>> > >>> > >>> > >> I think I have seen an explanation of this before (maybe in a PIC > >> datasheet?). > >> > >> The total input capacitance would be affected by the parasitic > >> capacitance and that would would change the charge time of the ADC > >> capacitor. For any given input voltage, this will change how many coun= ts > >> occur for the same sample rate. Thus, note 2 states that the sampling > >> frequency would have to be reduced to compensate for the difference in > >> charge time. Lower sample frequency gives more time to charge and more > >> counts for a given input voltage. > >> > >> Richard > >> > >> > >> -- > >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > >> View/change your membership options at > >> http://mailman.mit.edu/mailman/listinfo/piclist > >> > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .