AFAICS, the footnote is self explanatory. "To remedy this fADC should
be reduced".
The larger the capacitance, larger the acquisition time, or in other
words time taken
to charge that capacitor.

To maintain the nyquist sampling rate, you need to reduce the sampling
frequency,
eventually affecting bandwidth, as you guessed.

Cheers,

Manu



On Wed, Aug 22, 2018 at 1:36 AM, Jason White
<whitewaterssoftwareinfo@gmail.com> wrote:
> A footnote (note 2 in attached image) in the STM32F207 datasheet (page 12=
7)
> states that a high capacitance at the ADC input pin can reduce conversion
> accuracy. How exactly should this be interpreted?
>
> Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. Bu=
t
> will the capacitance affect the internal operation of the ADC?
>
> --
> Jason White
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