But that explanation only makes sense if the parasitic cap were on the ADC side of the sample-and-hold switch. Once you place it externally, it should only help, and the sampling frequency or sample-and-hold aperture are pretty immaterial to it. On Tue, Aug 21, 2018 at 8:08 PM, Richard wrote: > > > On 8/21/2018 4:06 PM, Jason White wrote: > > A footnote (note 2 in attached image) in the STM32F207 datasheet (page > 127) > > states that a high capacitance at the ADC input pin can reduce conversi= on > > accuracy. How exactly should this be interpreted? > > > > Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. > But > > will the capacitance affect the internal operation of the ADC? > > > > > > > I think I have seen an explanation of this before (maybe in a PIC > datasheet?). > > The total input capacitance would be affected by the parasitic > capacitance and that would would change the charge time of the ADC > capacitor. For any given input voltage, this will change how many counts > occur for the same sample rate. Thus, note 2 states that the sampling > frequency would have to be reduced to compensate for the difference in > charge time. Lower sample frequency gives more time to charge and more > counts for a given input voltage. > > Richard > > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .