I am in the same frame of mind as Jason - I don't see how this could affect
DC accuracy. Yes, the sample and hold circuit will draw pulses of current
from the input but usually external capacitance there HELPS you because it
smooths out the pulses so you don't see as much voltage drop across Rin.
Maybe they are referring to situations where the cap resonates with the
trace inductance and there is ringing after each charging pulse?

On Tue, Aug 21, 2018 at 5:24 PM, Ryan O'Connor <rocifier@gmail.com> wrote:

> You can see Cparasitic is on the same input line as C(ADC). If you have
> parasitic capacitance on the input, it will add to the capacitance of
> C(ADC) and affect the internal timing circuit of the sample and hold
> feature of the ADC. So to answer your question, yes it will affect the
> internal operation.
>
> Ryan
>
> On Wed, 22 Aug 2018 at 08:09, Jason White <whitewaterssoftwareinfo@
> gmail.com>
> wrote:
>
> > A footnote (note 2 in attached image) in the STM32F207 datasheet (page
> 127)
> > states that a high capacitance at the ADC input pin can reduce conversi=
on
> > accuracy. How exactly should this be interpreted?
> >
> > Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.
> But
> > will the capacitance affect the internal operation of the ADC?
> >
> > --
> > Jason White
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