So no real issues it seems with having 12v tracks sitting directly above 5v tracks. However a sprinkling of 10uf capacitors along the 12v trace with some ceramics near the switcher. I will assume ceramics near and on the output of the switcher and others near the input to the devices it is supplying. And 10uf caps near and on the input to the switcher. Cheers justin On 28 June 2018 at 13:33, Randy Dawson wrote: > Well heck, make that 500mA trace as large as possible, and decap it to th= e > gnd plane with a bulk (10uf) and several ceramic NPOs near the switcher, = on > a plane to the pin and very nearby, with vias to gnd. > > > ________________________________ > From: piclist-bounces@mit.edu on behalf of > Justin Richards > Sent: Wednesday, June 27, 2018 8:36 PM > To: Microcontroller discussion list - Public. > Subject: [EE]: 2 layer PCB layout. 12v and 5v tracks stacked. Good or bad > > Working on a 10cm x 10cm board. > > Vin is 12V, gets converted to 5v and 3.3v. > > Bottom plane is ground and top layer will be 3.3v flood. > > As always, space is constrained. > > I have routed the 12v (Vin) 2mm trace on the top layer around half of the > perimeter. > > I want to route the regulated 5v 2mm trace directly underneath the 12v > trace. > > Is this a bad idea. Should the 5v trace be routed such that it also runs > on top of the ground plane. > > The 12v trace will be supplying an inductive load that gets switched on a= nd > off and draws about 500mA. > > Attached top half of the brd. Tried to make attachment as small as > possible. > > Cheers justin > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .