A fun thought: I have a PCB with six layers. I am looking for ways to minimize capacitive= coupling between tracks on the top and tracks on the bottom. If I think of the tracks as parallel plates, and the PCB as the dielectric,= then that gives me a certain C, a bit bigger than suggested by the directl= y overlapping area. Now what happens if I put a small copper dot, floating, in layer 3 or 4? = It seems like this should create a series pair of capacitors of about twice= the value, and no net change, but I keep thinking that the end result has = to be a little less C than the first case. Is there something freeware-ish that I can use to model a three (or more) p= late capacitor where the middle plates are floating? -- David VanHorn Lead Hardware Engineer Backcountry Access, Inc. 2820 Wilderness Pl, Unit H Boulder, CO 80301 USA phone: 303-417-1345 x110 email: david.vanhorn@backcountryaccess.com --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .