Hi all,

I would assume that some of you are using the ARM processors produced by
Freescale (now NXP) in their "Kinetis" line. I am working on a project
using the MK20DX256VLH7 which is an ARM Cortex M4 with 256KB flash and a
host of peripherals. It is a pretty amazing chip and my first venture into
ARM territory. I am using a Teensy 3.2 module, an Arduino-compatible
device, which contains this processor.

I'm very happy with the processor itself so far but the NXP/Freescale
documentation is horrible for this part. I feel the need to rant a bit and
see if my experience is common. I am used to the evil which lurks in the
Microchip datasheets (references to info found only in other documents
which only partially applies to your chip, specs which are never declared
valid but go straight from "preliminary" to "not recommended for new
designs", etc.) but I didn't expect to have similar problems with this
because I've had fairly good experiences with Freescale Power-PC-based
processor documentation.

The first problem I've had is that there doesn't seem to be any overall
guide to the manual, which is needed because it is 1400 pages long. It took
me a long time to realize that you not only had to enable peripherals but
you also have to enable the clock path to each peripheral, which is listed
under a section called "System Integration Module" and there is no warning
under, say, the ADC section that you need to enable its clock in the "SIM".
Not only that but you have to enable the clock FIRST and then the
peripheral's own enable.

The second problem is that signal names are mentioned in peripherals and
then never mentioned again anywhere in the entire 1400 page document, so
that you don't know what other internal signals those connect with. For
example, the ADC has both a hardware trigger ADHWT and "hardware trigger
channel selects" called ADHWTSn where n can be A or B on this chip. It
turns out that these connect to "pre-trigger" signals coming from the
Programmable Delay Block, but it never says that anywhere. I had to figure
it out from guessing and inference.

Thirdly, much of the wording is very vague. In one spot it says:

PDB channel's corresponding pre-trigger asserts when the counter reaches
the channel delay register *and* one peripheral clock cycle after a rising
edge is detected on selected trigger input source or software trigger is
selected and SETRIG is written with 1.

The asterisks around AND are mine. What they really mean here is OR,
because EITHER of the two conditions they specify can assert the
pre-trigger. (as an additional issue, SETRIG should really be SWTRIG)

They also use the term "ping-pong operation" to refer to what is usually
called "round robin". I've never heard of ping-pong ever including more
than two states.

These are only a few examples of the problems which made it take two days
for me to get hardware-triggered ADC working.

Anyone else have similar problems with this NXP/Freescale ARM documentation=
?

Sean
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