I do use this technique but I have not done actual testing to determine how
much difference it makes. However, on paper it looks beneficial.

Bear in mind that we are really talking about two different reasons for
bypassing here: circuit reliability and EMC (electromagnetic compliance).
David's technique is really mostly about the EMC part. Depending on the
exact circumstances his technique may help or slightly hurt the circuit
reliability part. It can almost always be done in a way which doesn't
negatively impact circuit performance.

David's technique is about minimizing the amount of high frequency current
flowing in paths which are long enough to have significant radiation
resistance (i.e. "make good antennas"). Such a path need not be in a trace
- it could even be in a plane.

The circuit performance aspect focusses on minimizing the impedance (and
the Q factor) of the power and GND nodes as seen by the chip, so that
supply current pulses do not cause droop or "ground bounce".

Sean


On Mon, Dec 4, 2017 at 3:48 PM, Ryan O'Connor <rocifier@gmail.com> wrote:

> I have a question about this... is there really a difference between "rou=
te
> so that power goes THROUGH the capacitor pad on its way to the chip" and
> not? Does anyone have empirical evidence of this working vs not? Or is it
> just something people have imagined?
>
> Just curious as have not seen any tests around which prove the need for i=
t.
>
> Ryan
>
>
>
>
> On 5 December 2017 at 07:16, Van Horn, David <
> david.vanhorn@backcountryaccess.com> wrote:
>
> > Plenty of good answers, and I'll throw in a "HELL YES" as well.
> >
> > I saw one instance of a product in production using an Atmel AVR, where
> > there is a single pin which is an ADC AREF input only rather than a ful=
ly
> > implemented I/O pin.
> > The application didn't use the ADC at all, and the designer thought he
> > didn't need that bypass cap.
> > There was a box of boards which had failed production test, which had
> > resisted all attempts to repair.
> > I added the specified bypass cap and recovered 100% of those boards.
> >
> > If the data sheet specifies bypass caps, design them in.  If it doesn't=
,
> > design them in anyway, you can always DNP (do not populate) in
> production.
> >
> > Bypasses are your friend.  Route them well, and don't skimp.   I use X2=
Y
> > caps in critical applications. With any type of bypass cap I route so
> that
> > power goes THROUGH the capacitor pad on its way to the chip, and the
> ground
> > side of the cap returns directly to the nearest ground pin on the chip.
> > Never a "tee" where the current has the option to go past the cap.
> >
> > Similarly with crystal loading capacitors, where I route them directly =
to
> > the nearest ground pin on the chip and nothing else touches that trace
> > until it joins all the ground pours at the chip ground pin.
> > I have seen boards fail FCC testing hard because crystal caps were
> > "grounded" into a 100 mil ground track that was about a quarter
> wavelength
> > long at 400+ MHz.  The "ground" actually worked more like a shunt fed
> > antenna. :-P
> >
> >
> >
> >
> >
> > --
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> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> >
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