I like the decoupling tutorial page which Byron linked to. I also did a
little LT Spice simulation to illustrate the difference which decoupling
makes.

This simulation is based on the 74HC series output cell model given at the
end of this library:
https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk12/l35/11.1/7=
4hc.lib

The simulation is for a single 74HC series type output cell which is
roughly similar to what would be at the output of your oscillator. The
simulation has 100nH of inductance between the Vdd pin and true 3.3V, and
100nH between Vss and true GND. This represents about an inch of typical
PCB trace. The pulsed source inside is supposed to simulate the internal
oscillator circuit and is therefore referenced to the local internal Vss
net of the chip. I have given it a 15pF load which is the output load given
in the oscillator datasheet as typical. I show a 10MHz output. For many
cmos devices, the output stage dominates the pulsed load from the power
supply since it drives a much larger capacitance than internal nodes do.

Here's the simulation with only stray capacitance (10pF) as the bypass
capacitance:

https://s8.postimg.org/niw5n96at/Screenshot_from_2017-12-02_21_33_24.png

The green trace is the output waveform and the blue is the local Vdd-Vss
difference seen by the other internals of the chip. The ringing caused by
the pulsed supply current drawn from the rails interacting with the stray
inductance and capacitance is about 1.5V peak which could be enough to
cause glitches or other disturbances to the internal circuitry.

Here's the result with a 100nF bypass capacitor directly across Vdd, Vss:

https://s8.postimg.org/l1keg3had/Screenshot_from_2017-12-02_21_34_06.png

The ringing and ripple has almost disappeared from the power rails and the
output of the oscillator is cleaner, too.

Sean



On Sat, Dec 2, 2017 at 7:40 PM, Byron Jeff <byronjeff@clayton.edu> wrote:

> Comments embedded inline...
>
> On Sat, Dec 02, 2017 at 07:18:48PM +0100, Electron wrote:
> >
> > Hello,
> > it may seem a banal question, but as it's the first time I use an
> external
> > oscillator (with integrated crystal), I am not sure. The datasheet make=
s
> no
> > mention whatsoever to the need to use a bypass capacitor in the power
> line:
> >
> > https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
> >
> > But is this truly the case?
>
> Yes. The requirement is so prevalent that it's seldom explicitly mentions=
..
>
> >
> > Should I put a (100nF?) bypass capacitor anyway in your opinion?
>
> Always. This tutorial discusses why it is needed, choosing appropriate
> values, and different types of noise management and isolation:
>
> http://www.thebox.myzen.co.uk/Tutorial/De-coupling.html
>
> >
> > Space on the board may be used for something else otherwise, so I don't
> > want to put useless components. But then again who does.
>
> Never useless.
>
> >
> > Also, I guess there's no advantage in grounding the metalcase on this
> > integrated oscillator, like I use to do with Xtals. Maybe it's already
> > grounded but I haven't received it yet.. I ask in case it's not.
>
> Generally a canned oscillator will have a ground lead. So it's not
> necessary so add an additional one.
>
> > Thank you.
> > Kind regards,
> > Mario
>
> No problem. Hope this helps,
>
> BAJ
> --
> Byron A. Jeff
> Associate Professor: Department of Computer Science and Information
> Technology
> College of Information and Mathematical Sciences
> Clayton State University
> http://faculty.clayton.edu/bjeff
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--=20
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.