The closest I can get is shorting the gate to Vdd, however there is still some voltage drop across Rd, and in the real world that would fry the gate to channel junction. -- Sincerely, James Burkart *Filmmaker & Documentarian* *Burkart Studios* 925.667.7175 | Personal 415.738.2071 | Office *Web:* burkartstudios.com *Facebook:* facebook.com/burkartstudios On Mon, Sep 11, 2017 at 8:37 PM, James Burkart wrote: > Sure thing! > > I saved the lab to a word doc and put it on my Google Drive. > https://drive.google.com/file/d/0Bw1n2tiO8ikQVzlaekYyblVYaXM/ > view?usp=3Dsharing > > -- > Sincerely, > > James Burkart > *Filmmaker & Documentarian* > > *Burkart Studios* > 925.667.7175 <(925)%20667-7175> | Personal > 415.738.2071 <(415)%20738-2071> | Office > > *Web:* burkartstudios.com > *Facebook:* facebook.com/burkartstudios > > On Mon, Sep 11, 2017 at 8:31 PM, Sean Breheny wrote: > >> Could you post a photo of the original problem so we could see if someho= w >> you are interpreting it differently than we would? >> >> I just tried the physical circuit (I used a J310 because I don't have a >> 2N4860 and J310 seems very similar) and I can't get anything like the >> voltages they describe by making any one resistor open or shorted, >> regardless of whether I use a 10Mohm input impedance voltmeter or a 10G >> ohm >> impedance voltmeter. If I open the source resistor and measure Vs, I get >> about 3V with either the Rin=3D10Mohm meter or the Rin=3D10Gohm meter. >> >> >> On Mon, Sep 11, 2017 at 9:04 PM, James Burkart >> wrote: >> >> > Actually I meant Vgs closer to 0V, not Vg. >> > >> > -- >> > Sincerely, >> > >> > James Burkart >> > *Filmmaker & Documentarian* >> > >> > *Burkart Studios* >> > 925.667.7175 | Personal >> > 415.738.2071 | Office >> > >> > *Web:* burkartstudios.com >> > *Facebook:* facebook.com/burkartstudios >> > >> > On Mon, Sep 11, 2017 at 7:02 PM, James Burkart < >> james@burkartstudios.com> >> > wrote: >> > >> > > Raising the value of Rs serves to increase negative biasing the gate= , >> > > which raises the value of Vds. Lowering it brings Vg closer to 0V, b= ut >> > > increases Id, and increases the voltage drop across Rd. >> > > >> > > Opening Rs pulls Vg to ~-5V, and the transistor is in cutoff. In thi= s >> > case >> > > I do get 15V at Vd since there is virtually no current through the >> > > transistor (spice simulation shows 177pA) but then Vds becomes ~10V. >> > > >> > > -- >> > > Sincerely, >> > > >> > > James Burkart >> > > *Filmmaker & Documentarian* >> > > >> > > *Burkart Studios* >> > > 925.667.7175 <(925)%20667-7175> | Personal >> > > 415.738.2071 <(415)%20738-2071> | Office >> > > >> > > *Web:* burkartstudios.com >> > > *Facebook:* facebook.com/burkartstudios >> > > >> > > On Mon, Sep 11, 2017 at 1:10 PM, Dwayne Reid >> > > wrote: >> > > >> > >> Hi there, Sean. >> > >> >> > >> You are forgetting about current that flows through the gate resist= or >> > >> to Ground. This is a J-FET, so the gate diode junction is forward >> > >> biased if Rs is open. >> > >> >> > >> Another possibility that Rs is very high value. I haven't bothered >> > >> to work out the math for the possible high value. >> > >> >> > >> dwayne >> > >> >> > >> >> > >> At 11:58 AM 9/11/2017, Sean Breheny wrote: >> > >> >I might be missing something but I don't think this problem is wel= l >> > >> >designed. I think we can narrow it down to Rs being open but >> > technically >> > >> it >> > >> >isn't possible, as far as I can see, to get exactly the voltages >> > >> mentioned. >> > >> >Vd=3D15V implies that absolutely no current is flowing from the >> supply, >> > so >> > >> >there shouldn't be ANY voltage drop across the drain-source >> connection. >> > >> > >> > >> >Here's my train of thought: >> > >> > >> > >> >If Rd were open, Vd would be zero. >> > >> >If Rd were shorted, the current would be limited by the negative V= gs >> > >> which >> > >> >would develop (I am defining negative Vgs as Vs>Vg, which reverse >> > biases >> > >> >the gate junction for an N JFET), so there would be some Vds drop = of >> > >> >several volts. >> > >> > >> > >> >If Rg were open, I think the FET behavior would tend toward the >> Vgs=3D0 >> > >> >behavior where almost the maximum current flows, but then Vd would >> be >> > >> less >> > >> >than 15V. >> > >> > >> > >> >If Rg were shorted, the circuit would behave almost as if nothing >> were >> > >> >wrong, unless 15V was enough to cause reverse breakdown of the gat= e >> > >> >junction, but in that case Vd would be less than 15V since an >> excessive >> > >> >leakage current would flow. >> > >> > >> > >> >If Rs were shorted, Vs would be zero. >> > >> >If Rs is open, then we would expect Vds=3D0 (Vd=3DVs=3D15). This i= s the >> > closest >> > >> >to what we observe. In the real world, the 10Meg input impedance o= f >> a >> > >> >typical multimeter would probably produce something similar to wha= t >> is >> > >> >claimed here (it would act as a very high value of Vs) but Vd woul= d >> not >> > >> be >> > >> >identically 15V. >> > >> > >> > >> > >> > >> >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid < >> dwayner@planet.eon.net> >> > >> >wrote: >> > >> > >> > >> > > Hi there. >> > >> > > >> > >> > > Consider what happens if Rs goes open. Also consider that the >> gate >> > >> > > junction becomes forward-biased when Vgs goes negative. >> > >> > > >> > >> > > dwayne >> > >> > > >> > >> > > >> > >> > > At 06:40 AM 9/11/2017, James Burkart wrote: >> > >> > > >Hello all! >> > >> > > > >> > >> > > >I am working on a lab for a class and we are given a simple >> > >> self-biased >> > >> > > >N-channel JFET circuit: Rd =3D 4.7k, Rs =3D 1k, Rg =3D 2M, Q1 = =3D >> 2N4860, >> > >> Vdd =3D >> > >> > > >+15V. >> > >> > > > >> > >> > > >Then we are given the scenario: Vds =3D 66.5mV, Vd =3D 15V, Vs= =3D >> 14.9V. >> > >> > > > >> > >> > > >Assuming only one component can be bad, what is the likely >> problem? >> > >> > > > >> > >> > > >I built the circuit in MPLab and tried everything I could thin= k >> of >> > to >> > >> > > >recreate the voltages, but everything I tried does not work. >> > >> Shorting Rd >> > >> > > >was my first thought, but that also results in Vds being 12.6V= .. >> > What >> > >> am I >> > >> > > >missing? Can anyone get me on the right track? I have shorted >> and >> > >> opened >> > >> > > >all resistors, the only thing I can't do (or don't know how to >> do) >> > is >> > >> > > >recreate a faulty FET. >> > >> > > > >> > >> > > >-- >> > >> > > >Sincerely, >> > >> > > > >> > >> > > >James Burkart >> > >> > > >*Filmmaker & Documentarian* >> > >> > > > >> > >> > > >*Burkart Studios* >> > >> > > >925.667.7175 <(925)%20667-7175> | Personal >> > >> > > >415.738.2071 <(415)%20738-2071> | Office >> > >> > > > >> > >> > > >*Web:* burkartstudios.com >> > >> > > >*Facebook:* facebook.com/burkartstudios >> > >> >> > >> >> > >> -- >> > >> Dwayne Reid >> > >> Trinity Electronics Systems Ltd Edmonton, AB, CANADA >> > >> 780-489-3199 voice 780-487-6397 fax 888-489-3199 Toll Free >> > >> www.trinity-electronics.com >> > >> Custom Electronics Design and Manufacturing >> > >> >> > >> -- >> > >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> > >> View/change your membership options at >> > >> http://mailman.mit.edu/mailman/listinfo/piclist >> > >> >> > > >> > > >> > -- >> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> > View/change your membership options at >> > http://mailman.mit.edu/mailman/listinfo/piclist >> > >> -- >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> > > -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .