That was my second guess. Eliminating Rs reverse biases the FET at about -5V, and Vds is 10V. -- Sincerely, James Burkart *Filmmaker & Documentarian* *Burkart Studios* 925.667.7175 | Personal 415.738.2071 | Office *Web:* burkartstudios.com *Facebook:* facebook.com/burkartstudios On Mon, Sep 11, 2017 at 9:26 AM, George Smith wrote: > James Burkart wrote: > > > I am working on a lab for a class and we are given a simple self-biased > > N-channel JFET circuit: Rd =3D 4.7k, Rs =3D 1k, Rg =3D 2M, Q1 =3D 2N486= 0, Vdd =3D > > +15V. > > > > Then we are given the scenario: Vds =3D 66.5mV, Vd =3D 15V, Vs =3D 14.9= V. > > > > Assuming only one component can be bad, what is the likely problem? > > > What do you get if Rd goes open circuit and you measure the voltages > with an AVO8? :-) > > George Smith > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .