Dwane - no, for an n jfet the gate would only be forward biased if it were higher than the source in voltage (gate more positive than source). Jfets are always depletion mode devices so they are on with no gate bias and turn off when reverse bias is applied to the gate-channel junction On Sep 11, 2017 3:10 PM, "Dwayne Reid" wrote: Hi there, Sean. You are forgetting about current that flows through the gate resistor to Ground. This is a J-FET, so the gate diode junction is forward biased if Rs is open. Another possibility that Rs is very high value. I haven't bothered to work out the math for the possible high value. dwayne At 11:58 AM 9/11/2017, Sean Breheny wrote: >I might be missing something but I don't think this problem is well >designed. I think we can narrow it down to Rs being open but technically i= t >isn't possible, as far as I can see, to get exactly the voltages mentioned= .. >Vd=3D15V implies that absolutely no current is flowing from the supply, so >there shouldn't be ANY voltage drop across the drain-source connection. > >Here's my train of thought: > >If Rd were open, Vd would be zero. >If Rd were shorted, the current would be limited by the negative Vgs which >would develop (I am defining negative Vgs as Vs>Vg, which reverse biases >the gate junction for an N JFET), so there would be some Vds drop of >several volts. > >If Rg were open, I think the FET behavior would tend toward the Vgs=3D0 >behavior where almost the maximum current flows, but then Vd would be less >than 15V. > >If Rg were shorted, the circuit would behave almost as if nothing were >wrong, unless 15V was enough to cause reverse breakdown of the gate >junction, but in that case Vd would be less than 15V since an excessive >leakage current would flow. > >If Rs were shorted, Vs would be zero. >If Rs is open, then we would expect Vds=3D0 (Vd=3DVs=3D15). This is the cl= osest >to what we observe. In the real world, the 10Meg input impedance of a >typical multimeter would probably produce something similar to what is >claimed here (it would act as a very high value of Vs) but Vd would not be >identically 15V. > > >On Mon, Sep 11, 2017 at 12:57 PM, Dwayne Reid >wrote: > > > Hi there. > > > > Consider what happens if Rs goes open. Also consider that the gate > > junction becomes forward-biased when Vgs goes negative. > > > > dwayne > > > > > > At 06:40 AM 9/11/2017, James Burkart wrote: > > >Hello all! > > > > > >I am working on a lab for a class and we are given a simple self-biase= d > > >N-channel JFET circuit: Rd =3D 4.7k, Rs =3D 1k, Rg =3D 2M, Q1 =3D 2N48= 60, Vdd =3D > > >+15V. > > > > > >Then we are given the scenario: Vds =3D 66.5mV, Vd =3D 15V, Vs =3D 14.= 9V. > > > > > >Assuming only one component can be bad, what is the likely problem? > > > > > >I built the circuit in MPLab and tried everything I could think of to > > >recreate the voltages, but everything I tried does not work. Shorting Rd > > >was my first thought, but that also results in Vds being 12.6V. What am I > > >missing? Can anyone get me on the right track? I have shorted and opened > > >all resistors, the only thing I can't do (or don't know how to do) is > > >recreate a faulty FET. > > > > > >-- > > >Sincerely, > > > > > >James Burkart > > >*Filmmaker & Documentarian* > > > > > >*Burkart Studios* > > >925.667.7175 | Personal > > >415.738.2071 | Office > > > > > >*Web:* burkartstudios.com > > >*Facebook:* facebook.com/burkartstudios -- Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA 780-489-3199 voice 780-487-6397 fax 888-489-3199 Toll Free www.trinity-electronics.com Custom Electronics Design and Manufacturing -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .