Hi there. Consider what happens if Rs goes open. Also consider that the gate=20 junction becomes forward-biased when Vgs goes negative. dwayne At 06:40 AM 9/11/2017, James Burkart wrote: >Hello all! > >I am working on a lab for a class and we are given a simple self-biased >N-channel JFET circuit: Rd =3D 4.7k, Rs =3D 1k, Rg =3D 2M, Q1 =3D 2N4860, = Vdd =3D >+15V. > >Then we are given the scenario: Vds =3D 66.5mV, Vd =3D 15V, Vs =3D 14.9V. > >Assuming only one component can be bad, what is the likely problem? > >I built the circuit in MPLab and tried everything I could think of to >recreate the voltages, but everything I tried does not work. Shorting Rd >was my first thought, but that also results in Vds being 12.6V. What am I >missing? Can anyone get me on the right track? I have shorted and opened >all resistors, the only thing I can't do (or don't know how to do) is >recreate a faulty FET. > >-- >Sincerely, > >James Burkart >*Filmmaker & Documentarian* > >*Burkart Studios* >925.667.7175 | Personal >415.738.2071 | Office > >*Web:* burkartstudios.com >*Facebook:* facebook.com/burkartstudios >-- >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >View/change your membership options at >http://mailman.mit.edu/mailman/listinfo/piclist --=20 Dwayne Reid Trinity Electronics Systems Ltd Edmonton, AB, CANADA 780-489-3199 voice 780-487-6397 fax 888-489-3199 Toll Free www.trinity-electronics.com Custom Electronics Design and Manufacturing --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .