Like James C., I haven't used this chip or peripherals but this seems like = a question to ask on Microchip Forums (there is even a specific Waveform Co= ntrol forum) or raise a support ticket directly with Microchip...=20 It seems this is a relatively new chip so some shakedown is probably needed= - there is an errata with reference to the CWG - may be unrelated? http://ww1.microchip.com/downloads/en/DeviceDoc/80000698A.pdf Stephen -----Original Message----- From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf Of= James Cameron Sent: Friday, 4 August 2017 11:14 AM To: Microcontroller discussion list - Public. Subject: Re: [PIC] 16F18854 CWG Setup in Assembly G'day James, I've not used either of these chips, CWG, or PPS, but I've looked briefly a= t the two datasheets. Moving from PIC16F1508 to PIC16F18854 adds silicon IP for a peripheral pin = select (PPS) module. Block diagrams in the '18854 CWG section refer to sig= nal names in the IP rather than signal names exposed in registers or at pin= s. So my guess is that "Gx1OEx <3:0> bits" are internal signals; and the d= atasheet is in error at that point. On your related question; from the description of the '18854 PPS section, e= specially figure 13-1 simplified PPS block diagram, and section 13.3 on bid= irectional pins, it doesn't seem likely to me that your hitching of outputs= will affect the inputs. Consider them default-assigned, along with the ot= her inputs also default-assigned to RB0 and RB1. So if you don't want to use the CWGxIN signals, make sure you have not sele= cted them in the CWGxISM register. (per table 20-2). -- James Cameron http://quozl.netrek.org/ -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/chang= e your membership options at http://mailman.mit.edu/mailman/listinfo/piclis= t --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .