My apologies about the double-post, but Piclist Admin Bob Blick kindly remi= nded me I had neglected to add the required "[PIC]" tag on my first post an= d he suggested I repost with the tag. I'm curious if the dearth of replies indicates that no one on this list has= experience with Microchip "PPS"? Or is it that fewer and fewer now progra= m PICs in Assembly? :-) Regardless, I would appreciate hearing your helpful feedback. Many thanks, James Wages =20 ------------------------------ =20 Message: 2 Date: Wed, 02 Aug 2017 13:31:51 +0900 From: James Wages Subject: [PIC] 16F18854 CWG Setup in Assembly To: Message-ID: <35C6736D-D089-4BFA-B88B-275E382BF3F2@kiramek.com> Content-Type: text/plain; charset=3D"UTF-8" =20 I've successfully programmed the CWG on a PIC16F1508 in Assembly in the= past. I am now attempting to do the same on the PIC16F18854 chip, but the= re appears to be a datasheet error that is obscuring my path forward. Plea= se refer to "20.12 Configuring the CWG" on page 266 if the PIC16(L)F18854 d= atasheet (Rev.B): =20 http://ww1.microchip.com/downloads/en/DeviceDoc/40001826B.pdf =20 Specifically note the following 3 steps extracted from Section 20.12, w= hich are to be performed in sequence: =20 7. Configure the following controls.=20 =20 c. Set the output enables for the desired outputs.=20 =20 8. Set the EN bit. =20 9. Clear TRIS control bits corresponding to the desired output pins to = configure these pins as outputs. =20 =20 The "output enables" mentioned in 7c above is the main issue. You can = see an "Output Enables" section 20.4.1 in the datasheet, which makes refere= nce to "Gx1OEx <3:0> bits. That reference appears to be a datasheet error = insofar as "Gx1OEx" does not appear under any register in that entire datas= heet, nor can I find anything close to resembling "Gx1OEx" in the p16f18854= ..inc file. =20 That apparent datasheet error, in addition to the fact that many regist= ers used on the 16F18854 are different from the 16F1508, means I cannot sim= ply copy/paste my 16F1508 ASM code into my 16F18854 code. =20 Simply put, I'm trying to figure out the correct ASM code for CWG setup= sequence on the 16F8854. =20 For sake of comparing the CWG Setup between the two PICs I've mentioned= , Step-6 in Section 26.11 on page 285 of the 16F1508 datasheet makes it cle= ar that register CWGxCON0 is to be used on the 16F1508. But CWGxCON0 canno= t be used for that same purpose on the 16F18854. Even so, the basic concep= t SHOULD be the same; meaning, we need to ensure CWG1A, CWG1B, etc. are map= ped as Outputs. The 16F1508 does not have PPS mapping so it was easier for= me to figure out the CWG setup sequence in ASM on that PIC. I'm new to PP= S mapping with the 16F18854, but the 16F18854 datasheet indicates the follo= wing on the subject: =20 PPS Outputs are defined by RxyPPS, where Rxy =3D R + Port + bit (So PortA, bit0 =3D RA0PPS) =20 The 16F18854 datasheet also defines this: RxyPPS value for CWG1A =3D 0x05 RxyPPS value for CWG1B =3D 0x06 =20 So in theory, the ASM code I've written in the following GIST should as= sign CWG1A as an Output on RB0 and CWG1B as an Output on RB1, contingent on= my TRISB settings: =20 https://gist.github.com/JDW1/387838530f298e71f3c7182ff1c48930 =20 Does my code look correct? =20 =20 I now have a related question. Will my code unhitch the CWG1IN & CWG2I= N "inputs" which are default-assigned to RB0 and RB1 respectively? (My aim = is to make the NCO output the CWG input, so external CWG inputs are not nee= ded in my application.) =20 I would appreciate hearing your thoughts. =20 Thank you, =20 James Wages =20 =20 =20 =20 =20 =20 ------------------------------ =20 --=20 http://www.piclist.com/techref/piclist View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist =20 =20 End of Piclist Digest, Vol 157, Issue 2 *************************************** =20 --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .