On 29 Jan 2017 at 21:40, IVP wrote: > > It seems a bit strange to me to drive the gate of the mosfet from a sup= ply > > which is referenced to +16V and GND when the source of the fet is at >=20 > Well, as it's a P FET I was thinking upside down, but evidently not think= ing > hard enough and it's come out as part N FET drive >=20 > I've restored the circuit to how it originally was >=20 > https://www.flickr.com/photos/97814409@N04/albums/72157675978832174 >=20 > Output is 2.2V into 6R8 >=20 > Gate voltage is from 1.3V to 8.8V. The test circuit in the ATP106 d/s > shows gate drive from 0V to -10V, with source at 0V, which would be > 0 to +10 for an N FET. As I figure it then, my gate is reaching only a > relative -7.5V >=20 > So I should be taking the emitter of the BC327 to at least a couple of > volts below 0V if source is at +9V ? That would make the gate 11V > below the source Hi Joe, ATP106 datasheet talks about gate drive as low as 4.5V gate drive, though 1= 0V=20 obviously gives better Rdson. Gate cutoff voltage is specified at 1.5V min = to 2.6V=20 max (for 1mA drain current @ Vds =3D 10V), so your revised circuit & measur= ed gate=20 voltages of 1.3V and 8.8V seem within workable range. Even if interpreted=20 differently and the 1.3 and 8.8V were measured wrt 0V, then translating tha= t would=20 give Vgson =3D 9-1.3 =3D 7.7V, and Vgsoff =3D 9-8.8 =3D 0.2V, in other word= s still fine. Seems like drive circuit should be good enough. Sure some tweaking might he= lp but=20 doesn't seem like it would make the difference between working and not-work= ing. --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .