I have not been following this thread closely but saw the comment on
Miller effect. To me, Miller effect is an apparent multiplication of
capacity due to voltage amplification. Imagine we have a capacitor to
ground that has a reactance such that 1V at 1kHz yields a current into the
capacitor of 1mA. Now add an amplifier with a gain of -10 from the top of
the capacitor to the bottom (bottom of capacitor driven by amplifier
output instead of ground). Now, when we drive the top of the capacitor
with 1V, we are driving the bottom of the capacitor with -10V (10V with
phase reversed), and we have 11V across the capacitor. We now see 11mA
through the capacitor. To the voltage source, it looks like the capacitor
value has been multiplied by 11 since the current has gone up by 11 times.

Looking at Vgs, assuming an N channel FET, as Vgs increases, Vds
decreases. Capacitive coupling from the drain to the gate would decrease
Vgs, not increase it. One possibility for gate failure is inductance in
the source lead. When the FET is turned off, the gate voltage goes to zero
and the source voltage could go substantially negative due to inductance
between the source and ground. I've dealt with this by adding resistance
in series with the gate so that gate to source capacitance pulls the gate
down with the source. This does slow the circuit down, though, especially
due to the above discussed Miller capacity. You can really see this by
watching the drain voltage. When the FET is turned on by driving the gate
positive, the drain voltage will come down, but Cdg will then drive the
gate voltage down tending to turn off the FET. As I recall (it's been
years since I worked on this), the voltage drops, tends to plateau, then
drops to ground.

Good luck! I blew out a lot of FETs!

Harold



--=20
FCC Rules Updated Daily at http://www.hallikainen.com
Not sent from an iPhone.
--=20
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
.