It's late at night...... This listing might be better to read list P =3D PIC18F1320 ; include "P18f1320.inc" t_data =3D 0x1800 CBLOCK 0X80 temp0 temp1 bitcntL bitcntH dg10 dg01 buffer ENDC mov macro val,file movlw val movwf file endm org 0x0000 ; write 64 bytes to buffer mov .64,bitcntL lfsr FSR1,buffer fillBuff movff bitcntL,POSTINC1 decfsz bitcntL goto fillBuff ; write to first data block movlw .0 movwf dg01 movlw .0 movwf dg10 call blk_add ;get block start address ;Erase block erase bcf EECON1,CFGS ;erase block bsf EECON1,EEPGD bsf EECON1,WREN bsf EECON1,FREE bcf INTCON,GIE mov 0x55,EECON2 mov 0xAA,EECON2 bsf EECON1,WR nop ; ???????????????????? ; tblrd*- ; CAUSES TBLPTRHL =3D 0x17FF ???? ; ???????????????????? ; 8 loops for 8 bytes =3D 64 bytes mov .8,bitcntH ;'8-bytes' counter lfsr FSR1,buffer ;data to WRite ; write 7 bytes first Write mov .7,bitcntL copy7 movff POSTINC1,TABLAT tblwt*+ decfsz bitcntL bra copy7 ; do 8th byte - write the latch without post inc movff POSTINC1,TABLAT tblwt* ; write to ROM mov 0x55,EECON2 mov 0xaa,EECON2 bsf EECON1,WR nop ; set ready for next 8 byte block tblwt*+ ; do another 8 bytes ?? decfsz bitcntH bra Write ; yes ; no - all done bcf EECON1,WREN wait goto wait ;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ;Get Flash address from dg10:dg01, tens:units, 00d-30d blk_add rlncf dg10,W ;combine dg10:dg01 rlncf WREG rlncf WREG ;(dg10 * 8) + (dg10 * 2) addwf dg10,W addwf dg10,W addwf dg01,W ;+ dg01 movwf temp1 ;temp1 =3D (dg10 * 10) + dg01 clrf temp0 bcf STATUS,C ;* 64 rrcf temp1 rrcf temp0 rrcf temp1 rrcf temp0 bcf STATUS,C ;add 0x1800 base address movlw Low(t_data) addwf temp0 movlw High(t_data) addwfc temp1 clrf TBLPTRU ;Flash block address movff temp1,TBLPTRH movff temp0,TBLPTRL return end On Tue, Oct 11, 2016 at 1:54 AM, Anthony Nixon wrote: > I wrote this test program and simulated with MPLAB > > It writes values 64 down to 1 into a RAM buffer > > Then it writes those bytes to ROM from BCD address in dg10 and dg01 > > There were 2 faults that I think failed in your code > > (1) the tblrd*- instruction after erasing the ROM block causes an > invalid TBLPTR address - see below > > (2) If you execute the code as written in your code and the data > sheet, then the TBLPTR will be set to the next 8 byte ROM block > "before" the write takes place. The data will then be written to the > following 8 bytes in ROM which is wrong > > I modified the code to tblwt*+ the TBLPTR for the first 7 bytes then > it does a tblwt* on the 8th to keep the TBLPTR in the correct block > > The write then takes place followed by another tblwt*+ which sets the > TBLPTR at the start of the next 8 byte block and continues the process > until all 64 bytes are written. > > It works ok in MPLAB > > > You can probably optimize it further if you like. > > cheers > > Tony > > > > > list P =3D PIC18F1320 > ; > include "P18f1320.inc" > t_data =3D 0x1800 > CBLOCK 0X80 > temp0 > temp1 > bitcntL > bitcntH > dg10 > dg01 > buffer > ENDC > mov macro val,file > movlw val > movwf file > endm > > org 0x0000 > > ; write 48 bytes to buffer > mov .64,bitcntL > lfsr FSR1,buffer ;data to WRite > fillBuff movff bitcntL,POSTINC1 > decfsz bitcntL > goto fillBuff > ;multiply digits by 64 to find block, add t_data base > ; > ;eg > ;digits =3D 23 in =3D 05c0, + 1800 =3D 1dc0 > ;Erase block > ;Write buffer48 to block > ;WR_block movff buffer,POSTINC0 ;last byte received > movlw .0 ;display value, manual test > movwf dg01 > movlw .0 > movwf dg10 > call blk_add ;get block start address > ; clrf tblptru ;Flash block address, manual test > ; movlw 0x18 > ; movwf TBLPTRH > ; movlw 0x40 > ; movwf TBLPTRL > ;Block command can resolve to 8 bytes > ;Erase command can resolve to 64 bytes (x00,x40,x80,xc0 starts) > ;Erase block > erase bcf EECON1,CFGS ;erase block > bsf EECON1,EEPGD > bsf EECON1,WREN > bsf EECON1,FREE > bcf INTCON,GIE > mov 0x55,EECON2 > mov 0xAA,EECON2 > bsf EECON1,WR > nop > ; tblrd*- ; CAUSES TBLPTRHL =3D 0x17FF ???? > ;WRite RAM to Flash as 64-byte (8*8) block > mov .8,bitcntH ;'8-bytes' counter > lfsr FSR1,buffer ;data to WRite > Write mov .7,bitcntL ;byte counter > copy8 movff POSTINC1,TABLAT ;copy 8 bytes to WRite buffer > tblwt*+ > decfsz bitcntL ;byte counter > bra copy8 > movff POSTINC1,TABLAT ;copy 8 bytes to WRite buffer > tblwt* > mov 0x55,EECON2 > mov 0xaa,EECON2 > bsf EECON1,WR > nop > tblwt*+ > decfsz bitcntH ;8-byte counter > bra Write > bcf EECON1,WREN > wait goto wait ;done > ;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > ;Get Flash address from dg10:dg01, tens:units, 00d-30d > blk_add rlncf dg10,W ;combine dg10:dg01 > rlncf WREG > rlncf WREG ;(dg10 * 8) + (dg10 * 2) > addwf dg10,W > addwf dg10,W > addwf dg01,W ;+ dg01 > movwf temp1 ;temp1 =3D (dg10 * 10) + dg01 > clrf temp0 > bcf STATUS,C ;* 64 > rrcf temp1 > rrcf temp0 > rrcf temp1 > rrcf temp0 > bcf STATUS,C ;add 0x1800 base address > movlw Low(t_data) > addwf temp0 > movlw High(t_data) > addwfc temp1 > clrf TBLPTRU ;Flash block address > movff temp1,TBLPTRH > movff temp0,TBLPTRL > return > end > > On Tue, Oct 11, 2016 at 12:54 AM, Anthony Nixon wro= te: >> You have buffer and buffer48 defined >> >> Any conflict there? >> >> On Mon, Oct 10, 2016 at 11:12 PM, IVP wrote: >>>> Example: >>>> >>>> movwf EECON2 is the same as movwf EECON2,0 >>>> >>>> Is that a default compiler setting? >>> >>> I'd imagine so, or at least I don't ever recall setting it otherwise >>> >>> movlw 0x55 >>> movwf eecon2 >>> >>> disassembles as >>> >>> MOVLW 0x55 >>> MOVWF EECON2, ACCESS >>> >>> Similarly bsf eecon1,eepgd >>> >>> BSF EECON1, 0x07, ACCESS >>> >>> Joe >>> >>> >>> ----- >>> No virus found in this message. >>> Checked by AVG - www.avg.com >>> Version: 2016.0.7797 / Virus Database: 4656/13181 - Release Date: 10/10= /16 >>> >>> -- >>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive >>> View/change your membership options at >>> http://mailman.mit.edu/mailman/listinfo/piclist -- http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .