Alpha particles from the packaging can induce soft errors. Cosmic rays are also another cause of soft errors and are especially problematic in space applications. Cosmic ray errors were something thast we had to take into account when building equipment to be used in high altitude observatories such as Manau Kea On 6 September 2016 at 09:38, wrote: > During the early 1980s I serviced machines that had the original triple > supply 16k dynamic RAM chips in them. The RAM chips were mounted as 18 > chips on a daughter board giving 32k x 9 modules, which plugged onto a > mother board that had all the necessary buffers and control logic. > > Every so often a module would be sent in to the workshop with a hard > parity error. Sure enough you could run the memory test and a hard error > would be found at a single location. If ran the memory test every day the= n > the error persisted. > > However if the module was put on the shelf for a week or so then the erro= r > went away. My understanding from the literature of the time was that such > faults were known to be caused by a radiation particle (one of alpha, bet= a > or gamma, I can't remember which) that would manage to hit the > semiconductor in such a way that it would lodge in the oxide insulation o= f > the storage capacitor, leaving a charge on the capacitor. From then on th= at > bit would only ever show one state. The story seemed to be that the charg= e > was equivalent to around 16000 electrons, which was about what the charge > was on the capacitor when charged normally to one of the states. > > Powering the chip up every day never allowed the charge that had been > tunnelled into the oxide to leak away, but leaving it on the shelf > unpowered meant that the natural leakage of the oxide was enough for the > electrons that had tunnelled their way into the oxide to leak away over a > period of time and the memory came good again. > > I understood that part of the problem was the ceramic the chips were > packed in, some ceramics were natural sources of suitable radiation > particles that created the memory errors, along with natural radiation fr= om > the sun and various other sources of background radiation around us.. By > the time that technology had moved on to single supply 16k chips the > ceramic technology had also moved on and had been developed so it produce= d > less radiation and could help shield from background radiation, and that > sort of problem just steadily disappeared. > > > > > > > It wasn't necessary. But, even with the well established core ,memory > it was > > usual to use a single parity bit on each byte and our original intentio= n > was to > > continue that practice. but with the 64 bit word we were using that > meant > > that there would be eight parity bits and some bright spark - not me - > quickly > > realised that those bits could be better employed > > in a Hamming configuration. Semiconductor memory was very new in 1970 > > and > > we had some reservations about its robustness. > > > > On 5 September 2016 at 18:28, John Gardner wrote: > > > > > ... Hamming was revelation to me: such an elegant solution. > > > > > > In regard to the elegance of Hamming, I concur. > > > > > > I'm curious about why a Hamming implementation was necessary > > > > > > with RAM? (A question, no implied criticism...) > > > -- > > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > > View/change your membership options at > > > http://mailman.mit.edu/mailman/listinfo/piclist > > > > > > > > > > > -- > > __________________________________________ > > David C Brown > > 43 Bings Road > > Whaley Bridge > > High Peak Phone: 01663 733236 > > Derbyshire eMail: dcb.home@gmail.com > > SK23 7ND web: www.bings-knowle.co.uk/dcb > > > > > > > > > > *Sent from my etch-a-sketch* > > -- > > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > > View/change your membership options at > > http://mailman.mit.edu/mailman/listinfo/piclist > > -- > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > --=20 __________________________________________ David C Brown 43 Bings Road Whaley Bridge High Peak Phone: 01663 733236 Derbyshire eMail: dcb.home@gmail.com SK23 7ND web: www.bings-knowle.co.uk/dcb *Sent from my etch-a-sketch* --=20 http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist .