On Sun, Sep 04, 2016 at 02:40:47AM +1200, RussellMc wrote:
> Actual cct diagram always nice.
> Saves having to look things up.
> And may show things not realised.

http://dev.laptop.org/~quozl/20160904_160502-crop.jpg

(paper, camera, gimp)

> Staring under load?

Yes.  An LM2936Z-5.0 followed by 10uF capacitor and a PIC16F88.

> If so, what's it like at no load?

Good point, haven't tried disconnecting the load.

> Power rise time?

Is in the oscilloscope trace?

> I've seen devices where too low a risetime was fatal to clock
> starting.

Good point, but the clock does start.

> Also- does it misstart only after a pror OK run?

It always misstarts after no prior run.

> I've seen ICs that must power own for a signifcant period (say 10 minutes
> +) if certain powerdown conditions occurred. What happened was an interna=
l
> node conducted due to power down relative sequences and stored charge
> inside IC
> in locations with no formal discharge path. IC had to be left to allow
> charge to work out.
>=20
> In one case, shorting certain pins to true ground was needed for reset.
> This was in in-production  product and occurred after a die shring !!! :-=
(.
> Had to add a discharger PCB to truly short pin.

--=20
James Cameron
http://quozl.netrek.org/
--=20
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