Brent,

I like your idea.  But it seems impossible to implement.  See Table 24-1 on=
 page 258 on the data sheet regarding the CLC inputs (there are 4 CLC modul=
es):

http://ww1.microchip.com/downloads/en/DeviceDoc/40001609E.pdf

As Joe said and as the data sheet says, the CWG cannot feed the CLC.  Disap=
pointing!

------------

Joe,=20

I get the digest to this list, so my replies sometimes are out of synch wit=
h your newest replies to me. Sorry.

I'm not sure I fully follow your flow on using Comparators.  But what I can=
 say is that I want to stick with RC5 (pin 5) and RC4 (pin 6) for my comple=
mentary outputs to the H-BRIDGE, since those are designated pins for the CW=
G and since the CWG output cannot be reassigned (to my knowledge) to other =
pins.  And since the PCB will need to fix the same 2 pins to feed the H-BRI=
DGE, sticking with RC5 and RC4 is the right thing to do.  CWG1A is RC5 and =
RC4 is CWG1B (inverse of CWG1A, so when CWG1A clones the NCO input, CWG1B i=
s the inverted NCO output). =20

Since I have 4 CLC modules, and since CLC1 can be reassigned to RC5 and CLC=
4 can be assigned to RC4, I thought that using two CLC modules would be a m=
eans of generating my needed complementary outputs for the volume-reduced w=
aveforms.  But for some unknown reason, I simply cannot get the CLC1 and CL=
C4 modules to output on RC5 and RC4, even though I disabled CWG and have ch=
ecked and rechecked my code.  I'll give my code another once-over and if I =
still cannot find the problem, I will post my code to the list for your rev=
iew.  That may take a couple days, since I am busy right now.  For now, ple=
ase note "page 4" in the above mentioned data sheet, which shows pin assign=
ments.  Again despite having setup APFCON properly, I still can't get CLC o=
utput on RC4 or RC5.  Strange.

--James Wages

--=20
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