Hi all,

I finally found the cause of the glitch on the DAC output

Turned out to be Timer1

The ADC sampling period is set by

tosc      =3D 38400000
pload     =3D tosc/40000

where pload is what goes into PR1, the timer match register

pload was simply 1 too many. Adding pload =3D pload -1 fixed it

Infuriatingly simple, many many wasted hours looking in other
places. But I learned a lot by pulling it all apart, more than if I'd got
it right initially. So it wasn't the oscillator, it wasn't the ADC, it=20
wasn't
the DAC and it wasn't any weird combination of them all together

Obvious in hindsight, maybe, the datasheet says, more of a hint to
reduce the reload for the exact required period

Note 1: The PRx register resets one timer clock period only after
the TxIF bit is set.
2: The TxIF bit is set one instruction cycle after a period match.

Timer latency I've compensated for on other PICs, didn't even
occur to me this time

The subtle effect of Timer1 being 1 in 960 out makes sense now

Anyway, lesson learned - check everything, assume nothing

Joe=20



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