--_004_D379F0C3F1674C85A93CA6A577CF5DFDivp1_
Content-Type: text/plain; charset="iso-8859-1"
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Hi all,

I've returned to a problem of a few weeks ago. That being, a
glitch appears on the DAC output of my 33FJ64GP802's. It's
holding things up and I need to find out what the cause is

Below is the complete code and attached is the .hex file

This is what it looks like

http://home.clear.net.nz/pages/joecolquitt/click.jpg

(0.2V, 50us, 5ms is per division)

The glitches are regularly ~19.5ms apart, which doesn't change
with signal frequency. The polarity (about mid-rail) depends on
the default data for the DAC, eg 0x0000 or 0xFFFF. This seems
to imply that the ADC stops producing data. There's no disruption
to the LATB,0 toggling, implying that the t1_loop is always
executed. LATB,0 toggles with a 25us period, so the PIC speed
is OK

In the 4th frame of the 'scope capture, the glitch is present but
not clearly seen. The wave itself is a good representation of the
input, so it appears the ADC and DAC are synchronised

Could someone try the hex in a chip and see if theirs also has
the glitch. If I can rule out the chip then it's the code. So far I've
not found alterations to the code which makes any difference.

I've had problems with silicon on other PICs so not ruling it out.
My dsPICs are Rev 12291

The hardware is pretty simple. PIC, decoupling caps, 16MHz
crystal + 2 x 22pF. The input signal is DC-biased to mid-rail
(1.65V) with a capacitor and 2 resistors

TIA

Joe

-----------------------

Note that Timer1 interrupt code has been commented out. The program
runs the same and the glitch happens with either interrupt or loop

         .include "P33FJ64GP802.inc"

  .global __reset             ;program entry point
;  .global __T1Interrupt       ;Timer 1 ISR

;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
;        Configuration Bits
;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

         config __FOSCSEL,FNOSC_FRC                            ;7.37MHz
internal
 ;        config __FOSCSEL,FNOSC_PRIPLL                         ;HS crystal=
,
16MHz
         config __FOSC,FCKSM_CSECMD & POSCMD_HS                ;clock
switching, HS crystal + PLL
         config __FWDT,FWDTEN_OFF                              ;Watchdog
Timer off
         config __FPOR,FPWRT_PWR1                              ;no brown-ou=
t
reset
         config __FGS,GSS_OFF & GWRP_OFF                       ;no code
protect
         config __FBS,NO_BOOT_CODE                             ;no boot cod=
e
         config __FICD,JTAGEN_OFF & ICS_PGD2                   ;JTAG
disabled, ICSP comm channel 2

tosc      =3D 38400000
pload     =3D tosc/40000           ;Timer1 count @ 40,000 samples/sec, =3D>
pload =3D 960 =3D 25us

midpoint  =3D 0x0000               ;DAC mid-point default value

store_add =3D 0x0a00               ;0a00 - 0dfe =3D 512 16-bit samples
read_add  =3D 0x0c00
limit_add =3D 0x0e00

;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

           .text

          __reset:

init:      clr     LATA
           clr     LATB

;153,600,000 / 16,000,000 =3D 9.6 =3D 48/5

;16.000000 /5 *48 /4 =3D> 38.400000MHz

           mov     #0b0000000000000011,w0
;                     0                     ROI
;                      000                  DOZE
;                         0                 DOZEN
;                          000              FRCDIV (/1)
;                             00            PLLPOST (N2) =3D /2 =3D> 153.6 =
=3D>
76.8MHz Fosc
;                               x                                      =3D
38.4MHz Fcy
;                                00011      PLLPRE (N1) =3D /5, 16MHz =3D>
3.2MHz
;                                           FREF input frequency to PFD
           mov     w0,CLKDIV

           mov     #46,w0
;                     xxxxxxxx
;                             mmmmmmmm      PLLDIV =3D (46 + 2) =3D 48 * 3.=
2MHz
=3D> 153.6MHz
           mov     w0,PLLFBD               ;PLL multiplier (M)

;--------------------------------

;switch to HC + PLL

;Unlock OSCCONH

           mov     #3,w0                   ;NOSC =3D 011 (HS + PLL)
           mov     #OSCCONH,w1
           mov     #0x78,w2
           mov     #0x9A,w3
           mov.b   w2,[w1]
           mov.b   w3,[w1]
           mov.b   w0,[w1]

;Unlock OSCCONL

           mov     #1,w0                   ;OSWEN
           mov     #OSCCONL,w1
           mov     #0x46,w2
           mov     #0x57,w3
           mov.b   w2,[w1]
           mov.b   w3,[w1]
           mov.b   w0,[w1]

           btsc    OSCCONL,#OSWEN          ;switch done
           bra     $-2

;--------------------------------

           mov     #0b0000000000000001,w0
;                     -----------
;                                    1      AN0
           mov     w0,TRISA

           mov     #0b0000000000000000,w0
;                     00                    DAC
           mov     w0,TRISB

           mov     #0x0f00,w15             ;set Stack to 0f00-

           mov     #0x0000,w0
           mov     w0,CMCON                ;no comparators

           clr     PMCON                   ;PMP disabled

           mov     #0b1111111111111110,w0
;                                    0      AN0 only analogue input
           mov     w0,AD1PCFGL

           mov     #0b0000010011100000,w0
;                     0                     ADC module off
;                      x
;                       0                   continue in idle mode
;                        x                  DMA
;                         x
;                          1                12-bit (set when ADC off)
;                           00              integer out, 0000 dddd dddd ddd=
d
;                             111           clock source, auto-convert
(SSRC)
;                                x
;                                 x
;                                  0        manual sampling, write '1' to
SAMP to sample
;                                   0       sample enable (SAMP)
;                                    0      done
           mov     w0,AD1CON1

           mov     #0b0000000000000000,w0
;                     000                   AVdd, AVss
;                        xx
;                          0                do not scan inputs
;                           00              n/a for 12-bit
;                             x             DMA buffer fill status
;                              x
;                               xxxx        DMA address increments after
each conversion
;                                   x       DMA buffer fill mode, always
fill from start address
;                                    x      DMA alternate sample bit, alway=
s
Sample A
           mov     w0,AD1CON2

;Fosc =3D 38.4MHz, Tcy =3D 25ns

;Sampling time, Tsmp =3D SAMC<4:0> * Tad
;12-bit, minimum sample time 3 Tad
;12-bit, conversion time 14 Tad
;ADC clock =3D 117.6ns minimum (70292C.pdf p356)

           mov     #0b0000010100000101,w0
;                     0                     Conversion Clock Source bit,
ADRC, system clock (Tcy)
;                      xx
;                        00101              SAMC<4:0>, number of Tad for
sampling, 15
;                             00
;                               000101      Conversion Clock Select bits,
Tcy divider, 6 =3D> Tad =3D 150ns
           mov     w0,AD1CON3              ;
xxxxxx+1 Tcy =3D Tad

           mov     #0b0000000000000000,w0
;                     xxxxxxxxxxxxx
;                                  000      DMA buffer size, 1 word
           mov     w0,AD1CON4

;          AD1CHS123 n/a for 12-bit

;          AD1CHS0, channel 0 input select
           mov     #0b0000000000000000,w0
;                             0             Channel 0 negative =3D Vrefl (V=
ss)
;                                00000      Channel 0 positive =3D AN0
           mov     w0,AD1CHS0

;          AD1CSSL, ADC1 input scan select register low

           mov     #0b0000000000000000,w0
;                     0                     DACEN
;                      x
;                       0                   DACSIDL
;                        0                  AMPON
;                         xxx
;                            0              FORM, unsigned integer
;                             x
;                              -------      DACFDIV

           mov     #15,w1                  ;DACFDIV divider wanted
           dec     w1,w1                   ;actual value is wanted-1
           add     w1,w0,w0                ;153.6 / 15 =3D 40000 * 256 =3D =
10.24
           mov     w0,DAC1CON

           mov     #0b0000011110000000,w0  ;Auxilliary clock for DAC
;                     xx xx    xxxxxxx
;                       0                  ;SELACLK, Fvco is source clock
for divider
;                          111             ;APSTSCLR =3D Fvco/1
;                             1            ;ASRCSEL, 1 =3D primary osc is
clock source
           mov     w0,ACLKCON

           mov     #0b1010000010100000,w0
;                     1                     LOEN, left outputs enabled
;                      x                    -
;                       1                   LMVOEN, mid-point enabled
;                        xx                 -
;                          0                LITYPE, IRQ on empty/full
;                           0               LFULL, IRQ bit, FIFO full
;                            0              LEMPTY, IRQ bit, FIFO empty
;                             1             ROEN, right outputs enabled
;                              x            -
;                               1           RMVOEN, mid-point enabled
;                                xx         -
;                                  0        RITYPE, IRQ on empty/full
;                                   0       RFULL, IRQ bit, FIFO full
;                                    0      REMPTY, IRQ bit, FIFO empty
           mov     w0,DAC1STAT

           mov     #midpoint,w0
           mov     w0,DAC1DFLT             ;default data
;                                          ;0x0000 =3D signed mid-point
;                                          ;0x8000 =3D unsigned mid-point

;           mov     #0b0001000000000000,w0
;                      001                  Timer1 priority level (1,
lowest)
;           mov     w0,IPC0

           bset    DAC1CON,#DACEN          ;DAC on

           bset    AD1CON1,#ADON           ;ADC on

;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

skip_r:    clr     IEC0                    ;disable all interrupts
           clr     IEC1
           clr     IEC2
           clr     IEC3
           clr     IEC4

           mov     #0b1000000000000000,w0
;                     1                     not using nested interrupts
           mov     w0,INTCON1

           clr     INTCON2

           mov     #0b0000000000000000,w0
;                     0                     Timer1 off/on
;                      x                    -
;                       x                   idle
;                        xxxxxx             -
;                              0            gated accumulation disabled
;                               00          pre-scaler =3D 1:1
;                                 x         -
;                                  x        when TCS =3D 0
;                                   0       TCS, clock source, internal
;                                    x      -
           mov     w0,T1CON

           mov     #store_add,w8           ;0a00
           mov     #read_add,w9            ;0c00

           mov     #pload,w0               ;load Timer1
           mov     w0,PR1

           bclr    IFS0,#T1IF              ;clear Timer1 IRQ flag
           bset    T1CON,#TON              ;Timer1 on

;           bset    IEC0,#T1IE              ;enable Timer1 interrupts

;here:      bra     here                    ;wait here for IRQ

;------------------------------------

;          Timer1 ISR

;           __T1Interrupt:

t1_loop:   btss    IFS0,#T1IF
           bra     $-2

           bclr    IFS0,#T1IF

           mov     #pload,w0               ;reload Timer1
           mov     w0,PR1

;Note - if the **** instructions are commented out, the glitch goes away.
;But of course there's no input signal processing

           bset    AD1CON1,#SAMP           ;sample
****

           btss    AD1CON1,#DONE           ;
****
           bra     $-2                     ;
****

           mov     ADC1BUF0,w0             ;send ADC result to circular
buffer ****
           mov     w0,[w8++]               ;
****

           sl      w0,#4,w0                ;* 16
           mov     w0,DAC1LDAT             ;and also to DAC left

           mov     #limit_add,w0
           xor     w0,w8,w0                ;test for 0e00 limit
           bra     nz,do_dacr
           mov     #store_add,w8           ;reset to buffer start

do_dacr:   mov     [w9++],w0               ;fetch delayed data (0000 dddd
dddd dddd)
           sl      w0,#4,w0                ;* 16
           mov     w0,DAC1RDAT             ;send to DAC right

           mov     #limit_add,w0
           xor     w0,w9,w0                ;test for limit
           bra     nz,toggle
           mov     #store_add,w9           ;reset to buffer start

toggle:    btg     LATB,#0                 ;activity monitor, confirm 25us
T1 period

           bra     t1_loop

  .end

--_004_D379F0C3F1674C85A93CA6A577CF5DFDivp1_
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Content-Description: adc-dac.hex
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