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> In your application, you talk of copying the data out of the DMA
> buffer to a FIFO. I wonder if the DMA could be used to directly
> place the incoming data in the FIFO.

Thanks Harold

The data in the FIFO is being used by another application as well
as the PIC, and there's too much of it to store inside the PIC, so it
has to go out and come back in.

You mentioned 4 buffers. So can I have 2 buffers for the sending
out and 2 for the getting back in or would it have to be done the
following way with just 2, assuming that a block transfer between
the DMA and the FIFO can be done between ADC samples,
which it can in this application. And, as I understand it, DMA has
its own data buss and does not consume CPU cycles, so some
of the operations won't affect and won't be affected by s/w. The
time taken to fill a DMA buffer with ADC results will certainly be
much shorter than the time needed to read / write the same number
of SRAM bytes

>From the start, with an empty FIFO -

(1) Buffer1 picks up the ADC results. Buffer2 is inactive

(2) When Buffer1 is full, Buffer2 becomes active and gets ADC results

(3) Contents of Buffer1 are shifted out to the external RAM. Buffer1
is then loaded with the data coming out of the other end of the FIFO
and moves it to PIC RAM. The PIC then processes that data

(4) Buffer2 fills up and the s/w goes back to (2), with buffer names
swapped by the ping-ponging

I've done something similar with an SD card and RAM, filling and
reading alternate buffers without using DMA, so I know it's possible
with probably the least efficient way of all !!

Joe




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