On Wed, 2015-12-09 at 14:08 -0500, Sean Breheny wrote:
> Every ADC I've seen >1MSPS has been parallel output. In fact, it wasn't a=
ll
> that long ago that 500MSPS ADCs used exotic logic-type outputs (ECL
> variants).

I was looking at the block diagram, and it does have an SPI interface,
although when I looked at the datasheet it wasn't clear what the SPI
interface is used for.  In the datasheet they describe 2, JESD204B lanes
at 5GHz each, which gets you where you need for 500 MSPS.

--McD

>=20
> Sean
>=20
>=20
> On Wed, Dec 9, 2015 at 1:32 PM, John J. McDonough <mcd@is-sixsigma.com>
> wrote:
>=20
> > Recently I got a blurb from TI for a 500MSPS, 16 bit A/D.  It appears t=
o
> > be SPI.  Seems to me that translates to something like running SPI a
> > little over 8 GHz.  Is that even reasonable?
> >
> > --McD
> >
> >
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