Richard,


Did you try to avoid RMW issues by using a shadow for the I/O ports?
It is  possible to have RMW issues if then pin loading capacitance is
too high or with other mysterious conditions.

Instead of BCFing or BSFing the pins, do that in a file register and
then copy its value to the port.

eg.:

unsigned char    ShadowPortA    =3D 0x04;    // EN starts disabled (1)
....
PORTA    =3D ShadowPortA;
TRISA    =3D 0x00;
....
ShadowPortA    &=3D ~0x04; // Set EN =3D 0
PORTA    =3D ShadowPortA;
....

ShadowPortA    |=3D 0x04; // Set EN =3D 1
PORTA    =3D ShadowPortA;


Do not forget that both CMCON and ADCON1 must be set to 0x07.


Cheers,

Isaac



Em 20/10/2015 11:08, Richard R. Pope escreveu:
> Issac,
>      I tried setting ADCON1 to 6 and 7 to no avail. Next?
> Thanks,
> rich!
>
> On 10/20/2015 7:54 AM, Isaac Marino Bavaresco wrote:
>> Richard,
>>
>>
>> In this PIC for the analog inputs to be off, you must write 0x06 or 0x07
>> to ADCON1, not 0x00.
>>
>>
>> Cheers,
>>
>> Isaac
>>
>>
>> Em 20/10/2015 10:15, Richard R. Pope escreveu:
>>> Issac,
>>>       Nicola pointed this out and I changed CMCON from 0 to 7. There is
>>> still no activity on the en or r/s pins. Any more thoughts.
>>> Thanks,
>>> rich!
>>>
>>> On 10/20/2015 7:05 AM, Isaac Marino Bavaresco wrote:
>>>> Richard,
>>>>
>>>>
>>>> Did you turn off the analog comparators?
>>>> If not, do that with CMCON =3D 7;
>>>>
>>>> If the comparators are not disabled, RA0 through RA3 become analog and
>>>> they are read always as '0'.
>>>> That would create RMW problem if you change each bit individually,
>>>> because this PIC doesn't have LAT register.
>>>>
>>>>
>>>> Cheers,
>>>>
>>>> Isaac
>>>>
>>>>
>>>> Em 20/10/2015 09:36, Richard R. Pope escreveu:
>>>>> Issac,
>>>>>        The problem is going to be in the configuration of the 16f877a=
..
>>>>> There is no activity on the en or the r/s pins. Argh! I thought that
>>>>> this might be the problem. The clock is running. I have every reason =
to
>>>>> believe that the pins are not set for
>>>>> digital I/O. Here is the setup
>>>>> statements:
>>>>>            TRISD =3D 0;
>>>>>            TRISA =3D 0;
>>>>>            ADCON0 =3D 0;
>>>>>            ADCON1 =3D 0;
>>>>>            CMCON =3D 0;
>>>>> Any more thoughts on this?
>>>>> Thanks,
>>>>>



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